Field Kit

MeshSat Field Kit changelog: the go-box hardware, the V1 kits as built and the V2 carrier PCB set.

Generated from the commit history of the hardware repository meshsat-fieldkit (CERN-OHL-S-2.0): features and fixes, newest first, one section per tag, untagged work on the main branch under Unreleased. The release files are on the releases page. The V1 kits are bench and demo units. No V2 board has been fabricated, ordered or built, and nothing has been through a field deployment.

About the revA release (3 September 2026): the carrier set as prepared for the JLCPCB order. Its release page was updated in place through 6 September and its assets track the last of those updates; the tag itself points at the 3 September sources. Those in-place asset swaps are not commits, so they do not appear below.

Unreleased (main, last change 2026-09-16)

Features

vendor: the fabricator’s capability document is in the tree, and the annular ring has an authority (4b90ba4b)
tools: via_audit.py, and the via rule splits along the line of who can answer it (ab13233a)
tools: an open owner decision must arrive as costed options with a recommendation (4bc95ba5)
tools: the sweep runs the second tool of every two-tool rule, and stays read-only doing it (24f0d4c4)
tools: every gate in the catalogue maps to a rule, and a rule may name more than one tool (668848a8)
tools: derate.py, no part sits on a rail that can reach its rated voltage (713cfd0c)
pcb: the ground-via grid is declared per board from its own measurement (83dbb3e3)
tools: no hard gate without a false-positive analysis, and one owner per fact (187c76b2)
pcb: every signal net on all seven boards is classified by its spectral content, with its reason (63f6942a)
tools: the return-path rule asks what the signal’s spectral content deserves (2b18073c)
tools: gate_sweep.sh, re-judge a routed board under today’s rule set without touching it (e7bd076e)
tools: a manual verification is judged by rebuilding its record, not by trusting it (7ef56ae3)
tools: rule ENV-002 is a gate: no rating claimed in a public document without its test (d3def80f)
rules: the prototype-only unknowns are generated from the registry, so what only hardware can decide never reads as a pass (SGN-002) (e7cc7e8c)
rules: the ETA is computed from the gap register’s remediations and the measured route history, with its assumptions stated and its waits separated (88f97f7c)
rules: the rulebook, coverage and gap register are generated from the registry, with the per-board status pages; the truth table and the repository rules that keep gates and registry together (69a4608e)
rules: the Phase B coverage map and the computed board status (absence is never a pass); every verdict names its rule ids and the rule set it was taken under (a2daa8c9)
rules: the canonical PCB rule registry, its reader and its validator (56 rules over 34 domains, 294 rule-board pairs); the readiness manifest freezes promotion of pre-audit evidence (470e4088)
e: E11 routes with the ground-via grid before the route, measured on D first (9c4d8f06)
d: D12 routes with In2 as a ground plane and the ground-via grid before the route (measured: 0 open, 279 of 289 return vias); a solder jumper’s pads carry the class clearance before the route (c1164f5c)
agent: a placement arm reads the couple gap back off the board it placed (couple_gap.py: part-box and courtyard gaps per couple); PLACE_COUPLE_GAP 2.4 reads 1.80 mm between the parts (062d36f6)
tools: gnd_grid.py lays rule 2’s ground vias before the route where a board declares it (D12’s fixer found no site for 47 of 185); B declares PLACE_COUPLE_GAP 2.6 (38 of 48, legal, five measured cycles); decision 27 carries D’s anatomy (via transitions, one seam run) and the reading it asks for (acbad223)
tools: return_gaps.py prints the runs behind rule 1’s uncovered millimetres, with what sits on the neighbouring layers at each (716902a5)
gates: a return via may sit inside a ground pad with room for its ring, where crowded copper leaves no fill beside a signal via (02666dfb)
routeflow: the resolved phase reaches the chain; A’s profile declares the rail-planes measurement for A36 (075e9934)
route: FR_RAIL_PLANES keeps the rails’ locked bands and islands in the DSN as planes on their own layers, off until an A route measures it against rail_prune (e0cf897a)
agent: the experiment store (SQLite, WAL, a cycle with an exact arm set, one terminal result per arm, artefacts, metrics, reviews, promotions, the chained ledger as its export); a cycle id minted before the proposal travels through the spec, every row and the review; the verdict envelope names the tools tree and the policy (d8401a2a)
predictor: a plane pad with no path to its plane and a rail pour without its keep-out are read on the placed board, before a route (9f1d950a)
e: the In2 ground fill under every back-side signal, the power pours above it (decision 27; the previous commit named this and did not carry it) (b4fb3de3)
e: an In2 ground fill under every back-side signal (decision 27); a placement the chain’s gate refuses is an UNMEASURABLE arm, not an infrastructure failure; the loop reads the runner’s row names (4be59ace)
agent: the B placement run shape as a template, and the suite on a code-only archive as a script (b67c235c)
routeflow: the re-finish phases C18, D12, E10, A36, B20 and P5’s single-signal-layer route under the return-current gates; two red-team reports of 15 September filed (dfe16aed)
gates: the two return-current rules: a plane under every signal net, a ground via beside every signal via, placed by the finish and refused by the board gate (d937f675)
ecad: the schematic pages draw every net that stays on a page as wires between its parts and mark every signal that leaves a page with the pages it goes to; B’s shared area is sectioned by its generator headings; six netlists identical (c26f6a22)
a: A35 profile: the PA head keep-out and the second stitch prune, after A34’s two pour-gate items (2a3f28ab)
images: render set ten, the display screenshot on the glass in every view and the monitor rear block under the plate (488cc392)
ecad: readable schematics: a page engine draws every board as wired A3 pages of functional blocks (ICs as boxes with rails top and grounds bottom, passives on the pins they serve, decoupling rows, power symbols), proves the drawing’s connectivity before writing, and the build cuts the sheet into A3 pages; all six netlists identical; the render scene puts the lit display on the glass and the monitor’s rear block under it (47684b3d)
images: concept render set nine, the monitor glass level with the face plate and the boards of 15 September; the import set at A32, B19, C17, D11, E9, E5, P4; a heredoc rule (32eb49cb)
a: A34, the four necks A33 measured again: vias in Q2’s drain tab, a via row across the VBUS20 leg, the PA run doubled south of J_AB2’s pins, the In2 VBAT plane kept off U2’s escape fan (nopour) (86a68f01)
a: A33, the four necks A32 measured: VBUS20’s leg and column at 8 mm with four vias a shunt and a foot at the corner, In2 VBAT tongues under the PA head and the converter row, the VIN_RAW head grown north, a foot at J_PA’s pin (3b875fed)
tools: rail_prune: the router’s own copper on a rail the rail’s copper already carries comes off before the judgement, judged by connectivity per piece; declared for A (1bf3a3f4)
a: A32 closed to 0 hard and 0 unrouted by hand (CH_BTST1’s B.Cu dive ripped and re-laid, the VBUS20 link on B.Cu between the islands’ own vias); rails 8 of 12, the VBUS20 F.Cu island at 43 percent (b7e0d28f)
c: C17 re-cut without the stale legend; the final gate reads the folder ALL PASS, 38 of 38, six of seven folders pass (9507c6cc)
c: C17 cut, the first C deliverable: 0 hard, 0 unrouted, check ALL PASS, 1 of 1 rails MET, netlist 852 of 852, verify_deliverable 36 of 36 (de521f6d)
tools: the pair copper meets the DRC before the fanout and a refused pair comes off whole; the inner gap takes the cushion; the via in a station’s middle pad asks every layer; B declares its predictor as a report (6ee75eeb)
pcb-b: decision 24 delegated by the owner and taken, option 2: B’s pair hold judges the coupled fraction at 0.80 (2a38d31a)
pcb-c: C17, the forty test points sit beside the nets they tap (781476e7)
pcb-a: A31, A30’s copper with the slot islands’ column keep-outs, under the corrected supervisor (76074255)
pcb-c: C16 pre-lays the whole six-wire e-paper bus, because one lane taken by hand moved the shortage to the lines beside it (04f9bf40)
pcb-c: C15 routes with /EPD_SDA pre-laid (1e06e44a)
pcb-c: a long net the router will not take is laid before the router runs (ec6f9bb9)
pcb-a: the A29 profile (1a4be371)
pcb-a: A28, the routed board with its pairs matched and its last two connections closed (23a8481d)
pcb-c: C13 routes the same copper with the rip-up cost at 10 (9097230a)
pcb-b: the pre-router’s obstacle map can grow each obstacle by its own class clearance (d3afbf31)
pcb-a: the pre-router measures its two legs and gives the short one the difference back (84c598b8)
tools: the final gate pass, one table over every deliverable folder in the tree (ebc17082)
pcb-c: C12, more passes for the one connection the corridor would not give up (6508a4e9)
pcb-b: a current B quote folder, every BOM line coded or declared, and the 8 September one retired (d5000713)
pcb-e: E9 is cut, 0 hard, 0 unrouted, both rails MET and 36 of 36 deliverable properties (b7a06131)
ecad: A27 and E9, the profiles for the copper the routed boards asked for (06ae6489)
pcb-b: the underside may not sit under a fine-pitch part’s escape field, behind a knob until an arm grades it (2c07103c)
pcb-a: A26, the profile for the second density pass (8d3e7868)
pcb-e: E8, the profile for the VIN_RAW copper pass (466db629)
pcb-d: D11 is cut, owner ruling 15 implemented and measured (b01fef25)
pcb-p: P4 is cut, 0 hard, 0 unrouted, 3 of 3 rails MET (6d1b5a15)
ecad: routeflow profile p4, P3 measured clean at 3 of 3 rails (ee3f9669)
ecad: owner ruling 13, B’s nine overflowing regions resized for the pair-corridor margin (ef2ab18a)
ecad: routeflow profile d11, owner ruling 15 measured clean in an isolated tree (dd51bdb1)
ecad: route_one refuses a route that drops its board’s plane nets (333f736d)
ecad: routeflow profile c11, C with its USB class actually registered (b4ddd7b8)
ecad: owner ruling 15 on D, the class back to 0.5 mm and the rail in locked inner copper (2d025d1f)
ecad: routeflow profile a25, A with the power copper its density asked for (b9bc2ed3)
ecad: a joint is not a conductor, and every piece too short to be one is reported (f052d38f)
ecad: a via is judged on its own barrel, and the pour bar is applied to pour copper (721f55a9)
ecad: power copper for A24’s VBUS20 and +12V_HF, a wider PA band, a keep-out on the VBAT plane’s neck (595e1337)
tools: owner ruling 22, the density is judged on the conductor and not on a grid square (f98cbbd9)
tools: owner ruling 19, under 1.1x of the density bar counts as MET (8a2d80ca)
tools: density_probe, what is AT an over-density cell, and A24’s eight rails are four jobs (39ef1858)
ecad: 3D views of all seven current boards, and a retired pack leaves two silkscreens (c17fabe0)
ecad: EasyEDA Pro import archives for the CURRENT state of all seven boards (5be8e6e5)
tools: the current density decides alongside the drop, and ruling 15 is amended to outer copper (9633a337)
tools: direct_close tries the escape stub’s far end when the pad is walled in (82f17830)
tools: every board records its regions, and region_room reads the right generator (27218845)
pcb-b: B’s placed board is LEGAL, 0 hard of the fifteen types (dfbf51ed)
e: U5 leaves the assembly list, owner ruling 12 (3772d4ac)
tools: direct_close says what else it could have started from (739969f2)
e5: the dock block rebuilt at 2 oz, owner ruling 7 (00796e29)
pcb-p: P3 is re-cut, and every part on it is orderable (3f4f5bd2)
pcb-a,pcb-e: A24 re-cut and E7 cut, and boards A and E certify PASS (e0b04b73)
pcb-a: A24 is cut, with owner ruling 10’s capacitors and no re-route (bb6db97f)
tools: two ends on different layers are a hop, not a refusal (61324443)
tools: the schematic’s values onto a routed board, without touching copper (8958a957)
place: board A’s inner-layer use follows its own layer count (69ac58ca)
boards: the eight owner rulings of 12 September, applied (ba27f00d)
tools: layer_judge, the measurement P0 asked for, and never the change (26d2b6a4)
tools: tiers 2 and 2b, a model in the loop behind a fail-closed validator (53f23247)
place: B declares the couple gap that lays eight more pairs, and the chain reads it (3b6b6421)
place: PLACE_COUPLE_GAP, room at the stations the pairs are refused at (3396b2a6)
preroute: a leg refusal says where it was refused, and on which side of the station (a7d2bcca)
preroute: PAIR_LEG_RETRY, the corridor searched again where its own legs were refused (6025b956)
pcb-a: A24’s finished board, 0 hard and 0 unrouted with every pair matched (b41d34d8)
parts: the codes A24’s BOM was missing, read from JLCPCB on 12 September (3e2d5245)
preroute: PAIR_VIA_CANDS, because the via-site cap of twelve was never measured (ad9d3ba7)
preroute: PAIR_END_STRICT, the end stubs searched against the partner’s own copper (e765cda0)
tools: A’s stub router searches a 0.05 mm grid, and the stage carries a time limit (9d7ec087)
tools: the finish runs the direct closer where a board declares it, A24 with its number (070389bf)
boards: B lays its pairs with the board’s own via minimum, worth six pairs (97b4fa0b)
tools: direct_close, the closure the router stopped short of, proposed as geometry (2f7b34ef)
preroute: PAIR_VIA_MODE, because a 0.70 mm via pair cannot leave an 0.8 mm fan (178e0cdb)
tools: A24 declares the stitch pruner, with the number that justified it (8ef58231)
preroute: order the pairs by the contention of their planned corridor (1171bca1)
preroute: PAIR_ENTRY_STRICT, so what the entry guard costs can be measured against a DRC (8703e8b5)
cloud: the isolated-chain runner, so a measurement is not disturbed by the box clone or the mirror (c7a85a81)
a: A’s pre-route board with all three pairs laid and 0 hard (e70de8e2)
a,b: the wall USB pair takes a ribbon of its own, so every pair leaves its header on an end row (c18fb348)
preroute: a laid pair is refused if its copper lies on another net, and the verdict names what it hit (174c1c97)
preroute: a diving leg ends short of the station so the other leg’s fan has room (a573ac81)
preroute: every piece records the emission that laid it, and the own-legs verdict names it (16bd2673)
preroute: a twist between two fixed parts is reported, and the own-legs verdict names the copper (771b8b0e)
a,b: the ribbon’s three pairs all lay now, 0 of 3 to 3 of 3 (03a2c145)
d: D10 is cut, 0 hard and 0 unrouted, read back on all its properties (e79a4545)
pre-router: the legs may pass the pair’s own copper at its own station (89760f5d)
pre-router: the stub search’s own cap is a knob, not a constant (e31352fe)
d: D’s routed board and its regenerated schematic, tracked (df4dfd08)
pre-router: name every footprint the pass moves (d69d0787)
pre-router: ask the geometry before refusing a pair for one rasterised cell (de34d027)
e: E7, the dock strip cut and read back on all 35 properties (cb78249f)
p: P3 re-cut and verified, the first deliverable through the collapsed finish (c79459b6)
tools: ledger_verify, the standing check the plan named and nobody wrote (b98bddd5)
b: the measured best pair environment, recorded on the board and not as a default (fddf6b1b)
tools: stitch_prune, for the locked via the pour has abandoned (fe1da604)
boards: every board gets the continuation pass, not just A (02d95f36)
arms: every row says which host and which KiCad build it ran on (4824b89a)
arms: round two, the corridor slack sweep that round one asked for (f9d88efc)
tools: declared pad aliases, after netlist_board refused board E for eighteen drain pins (f1ede821)
routeflow: validate, a profile check that writes nothing and touches no host (8ef1976c)
tools: layer_audit.py, and the P0 evidence for every board’s layer count (c77cad4c)
routeflow: with the per-pass jar, no session at all is INFRA_FAIL and not a routing outcome (36af2d34)
routeflow: the C, D, E and P profiles call the one finish (1b31d6b9)
tools: compare the board with the netlist it was placed from (af86ff42)
arms: sixteen B19 arms against the two measured failure classes (705124a0)
tools: arms.py, many pre-router arms at once, each with a prediction and a judge that is not it (64a8f333)
tools: one finish, with the stage order that has reasons; five clones have the opposite (1b6704c9)
routeflow: preflight checks the fab-artefact pin (e1f9cf30)
routeflow: the journal is a chained ledger, not an append-only file (32998b42)
routeflow: the supervisor decides on verdicts, and the profile’s prediction is graded (2250dd10)
tools: verdict.collect, so a caller can ask whether every gate passed (fc0bea0c)
tools: the tamper-evident ledger, and the two things about it that are easy to get wrong (804253f0)
tools: the never-auto floor as a file, checked against a diff (a4d7cbdf)
tools: a pin on which files may write a gerber, a BOM, a CPL or an order set (9c824fd9)
preroute: the pass reports its own map seconds (7063c9db)
tools: board_diff.py, because cmp cannot tell you whether two runs made the same board (0b2b0b31)
tools: every journal row names the bytes it is about (85722ee9)
tools: one verdict channel: seventeen gates decide in a file, no driver reads prose (8dccb5e4)
parts: hand-fit purchase routes, and the four gates that never bit (35e6555b)
parts: the PowerPAK SO-8 land takes one part, the CSD19532Q5B (owner ruling 11 Sep) (1d6e9167)
tools: jlc_certify.py, every part on the shipped BOMs checked against JLCPCB with a date (4aabbed2)
vendor: seven of the fifteen open picks researched, with the manufacturer’s document for each (4ffbf639)
tools: currency as a dated check, and the two places status was declared now have to agree (ff02854f)
vendor: the five drawings that search could not reach now have OCR sidecars (c3fda8ff)
vendor: every document now records where it came from and what revision it claims (0b577fc8)
vendor: PARTS.md, everything V2 uses enumerated from three sources that must agree (e19f9299)
tools: the parts this design builds with against the documents we hold, and the geometry of every vendor model (81fba69c)
tools: a datasheet knowledge base over v2/vendor/, advisory only and off every verdict path (5f254654)
tools: the inner-layer pair geometry is per class, because only the 90 ohm class misses there (cd5b8e62)
tools: a pair takes the width its layer needs, because an inner layer is a stripline (a8a04c14)
tools: every benchmark row records the KiCad build, the Python version and the core count (c477dd7e)
tools: the impedance gate carries the 2D field solver’s numbers and says where each one came from (15501015)
tools: route with our 1.9.0 build by default, its output proved identical to stock (11051f36)
tools: patch Freerouting 1.9.0 to write its session after every pass, and pass it from route_one (6188e0be)
tools: the engine carries the project name and seeds its uuids from it, so a board regenerates byte for byte (7563bd77)
tools: kisch, the schematic engine in one module with a strict ic() and deterministic uuids; the P board is the first to import it (43824920)
tools: a run gets its own immutable directory with provenance, and a deliverable is promoted only after it reads back (0e43d237)
tools: a pair with no corridor at all is searched again with a slim one: a 2.54 mm header leaves 0.94 mm and the corridor asks 1.02 (2317a99c)
tools: the negotiator keeps every iteration’s plan, not only its own pick (15b5b3b8)
tools: negotiated-congestion pre-routing: pairs price the shared cells instead of fighting for them (d8fe7333)
tools: multi-pass pre-routing, the pairs that failed go first next time and the best pass wins (cb2d638c)
tools: the A placement’s fine-pitch margin is a knob too (0ae12e5d)
tools: the pre-router’s corridor search box is a measured knob (ccf330e3)
tools: the room the B placement leaves around a fine-pitch part is a measured knob (3a2056e2)
tools: the pre-router’s corridor slack over its legs is a measured knob (1d421853)
tools: a rip-up episode is a trial, kept only when it leaves more pairs laid than it found (7c19e911)
tools: pre-router debug: name the copper a leg hits, not just the point (e6779c8e)
tools: pre-router: PAIR_ENTRY_VIA ends a leg at an IC’s escape via instead of stripping the escape and entering the pad (1f601666)
tools: pre-router rip-up and retry: a failed pair takes the laid pairs out of its corridor and is laid again first (e8e41efa)
tools: the partition’s regions can be routed one at a time, each locking the last (19b1c322)
tools: an optional coarser grid for the long pairs, off until it is measured (1f0a0115)
tools: the pair pre-router lays the corridor as found when no smoothing clears (79c7ec25)
tools: pair_report.py, who blocked which pair and where, counted (b6c22aa3)
tools: B19, the phase that carries the I/O high-availability layer, with its chain, finish and probe profile (384ec20e)
ecad: the mesh radio is duplicated on slot 3 and the two cards share the antennas through a voted changeover (95ca54a9)
tools: the B gate checks the I/O ownership invariants, the safe states and the bearer spread (e5a93fb0)
sch: the I/O control plane, three STM32H753 supervisors on two CAN-FD fabrics with 2-of-3 majority voters (97c436fa)
tools: the host-selection switches take their place beside the hub they feed (fbb0b1af)
sch: the per-bank USB host-selection fabric, TMUXHS4212 and TS3USB221A, with the ring and its safe state (ace6f5e4)
cad: the face section drawing, and the render stack follows B16 down (a3298c18)
tools: a corridor that cannot be found says why: the search never began, the node budget ran out, or the map has no path (3101b1aa)
ecad: P3 released, the pack BMS with the decoupling floor plan; 0 hard, 0 unrouted, 36 of 36 deliverable properties (0a1f16a4)
tools: a pair stub may join any point of its own net’s escape, not only the via it aimed at (62555f99)
tools: the pre-router lays the long pairs first; alphabetical order decided which pair got the room (b8b6172f)
ecad: the whole set moves to A24 B18 C9 D10 E7 P3 with the decoupling floor-plan pass (922bf0d5)
tools: the decoupling floor-plan pass in all six placement generators, and the second pass wired into every chain (ec009ba0)
tools: declared decoupling takes its slot beside the pin before the packer fills the regions; wired into the D generator first (cfd3d232)
tools: the E board declares its decoupling as data, thirteen entries including the buck’s input loop (c3c21600)
tools: the B placement packs each differential pair’s two series parts as a couple, pads across the pair axis, read from the netlist (47f3d39b)
tools: the C board declares its decoupling as data, so the loop gate measures fifteen entries instead of none (ac0f39af)
tools: a profile may cap the optimiser passes; the panel board’s auto-route finishes in 14 minutes and the two default passes then ran past every limit (56e5251c)
tools: the compute board declares thirty decoupling assignments, validated through the generator (a6eca71b)
tools: the copper checks join the D and C gates, where they find a pour eaten to islands; a fill piece under 5 mm2 is a crumb, reported and not counted as a loose island (b3156b3f)
tools: the power board declares thirty decoupling assignments; every board carries the written reason its distances stand until the floor plan is ruled on (643b38eb)
tools: the power board’s converter blocks declare which capacitor serves which supply pin, where the block is built (f2e69f7b)
release: D9, the VHF mezzanine, clean under the full gate set: 0 hard of 15 types, 0 unrouted, +5V drop 1.78 percent, three pairs at 89 ohm against a 90 target and one too short to judge, contracts pass, deliverable verified on all 35 properties (9e2e61c4)
tools: stitch a pour island that has no via of its own net, accepted per via; D9’s front ground pour had eleven, one of 222 mm2 (b95cc694)
tools: the pad-to-plane closure tries a via in the pad then a dogbone past its tip, keeping the first that closes without cost (8ef7af69)
tools: the placement audit separates a pruned escape whose pad pre-laid copper already reaches from one that leaves the pad bare; on B17 only 8 of 84 were served (0773af6d)
tools: a decoupling distance may be accepted only through the board’s own bypass-allow.txt with a reason, the erc-allow idiom; the D board records why its sixteen stand (58b0c230)
tools: a pass that moves a declared decoupling capacitor to the first free spot within 3 mm of the pin it serves, reporting what cannot reach (df99ee7a)
tools: the D board declares which capacitor serves which supply pin, so the decoupling gate of Stage C finally has something to measure (7784882b)
tools: a 2D field solver for differential impedance beside the closed forms, the second opinion the record owes; openEMS is not packaged for the box and atlc is (92896e91)
tools: long fine-pitch rows escape by depth stagger instead of splay, so an M.2 socket’s 37 pads no longer throw their end pins 5 mm into the neighbours; B17’s five sockets go from 10 to 13 unescaped pads each to none and its placement gate passes (a298a806)
tools: a pad its own plane cannot reach after the route gets a via in the pad, reverted if the hard count rises; in every finish of the wave (19483e74)
ecad: EasyEDA Pro Gerber exports of the V2 set (A22, C7, D8, E6, E5, P2 and the unrouted B16 quote board), B16 introduction cleaned, notes on the stopped description clean-up (99c6765d)
tools: impedance judge: the pin fans within 3 mm of a pad are reported and not judged, up to 3 mm unreferenced is a note, a pair under 5 mm of judged length is SHORT (USB 2.0 rise time 500 ps, 75 mm of trace) (7e564659)
ecad: EasyEDA Pro imports of the V2 set (A22, B16 quote-only, C7, D8, E6, E5, P2): import archives, epro2 and schematic PDF exports, views, per-board import notes and README; order log 5.2 (81577a5d)
tools: pair pre-router: a 0.4 mm receptacle row keeps its escapes and the escape via is the station (B17’s legs into the CM5 pads shorted their neighbours) (67681856)
tools: dc_drop names the disconnected pieces of a rail (layers, extent, source or loads) when a load is unreachable (fe29f1d3)
tools: pair pre-router: a station with laid copper is never swapped, the P leg dives under the N fan where the fan still crosses (a through-hole pad takes it on the hop layer); D9 pull-downs beside the series row (9d30829d)
tools: the pair pre-router stubs every other pad of a pair net to the laid copper (Freerouting 1.9.0 does not hold a class to its layers); D9’s pulls beside their pairs on the top layer; appendix note (a5bcc08e)
pcb-p: P2 routed clean under the full gate set (0 hard, 0 open, three rails MET, contracts pass): the ground stitch grid on the underside pour, the 0.5 mm power class for the sense links, the intent’s current sinks; deliverable meshsat-pcb-p-revA-P2 (c560c6c6)
tools: impedance-derived pair geometries per stack (four-layer USB 0.30/0.20 on F.Cu, six-layer USB 0.127/0.127 and DIFF100 0.127/0.20 on F.Cu and B.Cu) in the generators, profiles and chains; suffixed pairs in the pre-router; the stack written before every finish’s read-back; contracts read the newest netlist of a board’s copy directories (c3151e2c)
tools: B17 (the HDMI switches fixed at 16 mm pitch, the pair pre-router for the USB and DIFF100 pairs on F.Cu and B.Cu in the chain), its finish and profile; the P2 stitch grid keeps clear of the bands and rule areas (34dc92af)
tools: C8 (1.0 mm rail class, the pair pre-router in the chain, a 3 percent budget for the panel 5 V) and P2 (a locked ground stitch grid on the underside pour, the two-layer coverage floor), their finishes and profiles (8bb2608b)
tools: pair pre-router lays D9’s four USB pairs with 0 hard on the pre-route board (entry runs as runs of their own, same-layer runs merged before the offset, fans swap crossing passives, direct legs between adjacent stations, a via in a middle pin’s pad); D9 port-2 resistors in line with the bridge; the A23 finish and routeflow profile (76be8ddd)
tools: A23 bands as single polygons per net and layer, rail pads joined solid, the intent names the real current sinks and per-rail budgets; pair pre-router: entry stations (straight and fan entries, stripped escapes, via in a middle pin’s pad), exact hop starts, walked-back via pairs, Douglas-Peucker smoothing, twist by the pad pairs’ normals; D9 series resistors face the hub (8c3908d5)
tools: D9 USB cluster on the top layer (hub, bridge, ESD, codec, crystals, every pair’s series resistors side by side beside their pins); the pair pre-router in the D chain; pull resistors are stubs, same-part sections skipped, via map on every layer, no blind straight stubs, crossing ends via beside the pad (19555919)
tools: A23 power copper (rule 3): shunts and monitors in their rail columns, converters south of the inductors, islands, bottom bands with keep-outs and stitch vias for the slot rails, PA, VIN_RAW (In3 dive under the VBAT trunk) and VBAT; power_copper.py; the gate tests every footprint against the nut keep-outs; the Stage E1 jitter rows (7613b04d)
tools: pair pre-router: pad-layer anchors, free via sites for the end stubs, per-end crossings, laid pieces as obstacles, station report; appendix 32.68 with the rule 1 and rule 2 numbers on D8 (e01f8e61)
release: order set rebuilt for A22, C7, D8, E6, P1, E5 plus a QUOTE-ONLY B16 line from the placed pre-route board, for the JLCPCB sponsorship quote (f065bba0)
tools: rule 3, the power-copper pattern of A21 as a shared module for the placement generators (bands with keep-outs, islands, spines, stitch vias, IPC-2221 widths) (02c3eb72)
tools: rule 2, a per-class layer rule in the DSN (FR_LAYER_RULES, routeflow layer_rules, the profiles); rule 1 in progress: pair_preroute.py lays a pair’s legs as locked copper on a smoothed centreline with stations, twists detected (19914e74)
tools: the intent layer and the electrical verdicts (Stage C), the measured placement predictor (Stage D), the learned-critic data tools (Stage E) (4a6db066)
tools: partition jobs confined to their region by keep-outs, strict net assignment (ec193b2f)
tools: partition reconcile: rip the boundary conflicts, close with the stub router (8eca62d2)
tools: partition stage two: lock the global session, route the regions concurrently, merge by net (5426a079)
tools: net-partition routing: DSN class rewrite per region, one-group Freerouting job, DSN export of a locked board (9b65f303)
tools: cont_route keeps the plane nets and power layers and reads FR_OIT (27521dd0)
release: E5 rebuilt from the final A22 routed clean on the box, deliverable meshsat-pcb-e5-revA-E5 (33785fba)
release: A22 (six layers, run 12 with the hand closures) routed clean on the box, deliverable meshsat-pcb-a-revA-A22 (cbe75988)
tools: hand_route.py (locked waypoint tracks with vias, DRC-tested on a copy); appendix: the A22 run 12 closures (737d26d6)
release: P1 (the pack BMS board) routed clean on the box, deliverable meshsat-pcb-p-revA-P1 (80eb2183)
cad: pack_4s.py, the built 4S pack’s printed enclosure for the east pocket (56 x 236 x 46, cell block pocket, the P1 board bay, lid) (209bb369)
pcb-p: P1 pack BMS board generators (BQ4050 SMBus gauge and protection for the built 4S pack, 70 x 44, 2 oz, the power path in locked bands), chain, finish and routeflow profile; the BQ4050 sheet filed (751200aa)
release: C7 (the panel backer ring) routed clean on the box, deliverable meshsat-pcb-c-revA-C7 (f96421aa)
tools: fix_c7_u3.py, the hand closure of the RP2040’s IOVDD pad inside the QFN ring on the C7 route (b938872b)
pcb-a: run 11 placement: INA226 row at 12 mm pitch, the front-end FETs beside their controller, wider support regions, 250 router passes (4c1d9dff)
tools: unknot.py removes the router’s two-net tangle before the stub router; wired into the A22, C7 and B16 finishes (c0e6e181)
pcb-a: A22 on the six-layer stack (In1 and In4 solid ground, In2 and In3 routable), title block fixed; vendor rows marked previous generation (4f4efcbb)
render: the QMX HF unit in its lid tray over the right strip, a lid-inside view (c1f01bc7)
render: scene for the MESHSAT-830 set (A22, D8 at the mezzanine site, B16 with three CM5 sites and the M.2 cards, C7 ring, Xenarc on the plate, PA flange, headset jacks, camera, eleven blind-mate paths) (d7645430)
ecad: E6 routed clean and released (dock strip with the sensor controller, In2 power planes, the pack cable on J_BATT pin 2) (5be7c8c5)
ecad: stub router closes at the project’s class width with a scalable search window; A22 run 8 narrows the power classes and moves the support parts under the mezzanine (4141df84)
cad: face plate v2 files and drawing for the C7 face, the QMX lid bracket, the D8 handoff row (1f46cf83)
cad: face plate v2 for the C7 face (Xenarc block cutout and VESA holes, headset jacks, camera window, light guide, PA nuts), the wall template from panel1450’s jack lists, E6 pack connector pin order (2306b0e6)
ecad: D8 routed clean and released (SA868 exciter, T/R relay, LPF, USB audio and control set), C7 generators (backer ring, RP2040 panel controller, PDi e-paper driver, Xenarc face, headset jacks), per-closure stub acceptance, plane-net fanout fixes (1e4af328)
ecad: D8 generators (SA868 exciter, T/R relay and LPF, USB audio and control set), E6 round-4 changes (In2 power planes, 0.4 mm escapes for the RP2040, fanout search widened), B16 placement duplicate fix and reference guard, escape pruning (bdfc7b3f)
ecad: B16 generators (three CM5 slots, PCIe and USB 3 fabric, Ethernet and HDMI switches, radios), A22 PowerPAK pin map and net-class fixes, E6 route relief, appendix 32.59 (273c5431)
tools: the Stage 4 gate is graded on the plain rows of each board’s newest pre-route; tables carry the pre-route hash (dd4f96d4)
tools: C6 keep-out board on 1.9.0 plainly, beside the stalling 2.4.1 production route (0071166a)
tools: plain experiment configurations (no settings block, the production route) for the Stage 4 A/B on every board (352ebb8a)
pcb-c: C6, the four-layer backer routed clean (0 hard, 0 open, 240 router vias); deliverable meshsat-pcb-c-revA-C6; order and review sets rebuilt with B15 and C6, B14 and C5 under superseded (03126d3c)
tools: C6 four-layer experiment adds the 2.4.1 rows without the power layer (the VM’s clean configuration) (77f89dbc)
tools: fr_rules --only to isolate which settings item costs the design’s clearances; B15 isolation experiment (e125d73e)
pcb-b: B15, the six-layer compute carrier routed clean under routeflow on Freerouting 1.9.0 (0 hard, 0 open, 294 router vias); deliverable meshsat-pcb-b-revA-B15 (1650a07e)
tools: C6 production profile routes on 1.9.0 with the In1 plane (Stage 4 rule: 2.4.1 did not complete) (8b75d5b1)
tools: C6 four-layer experiment file (7d91245a)
pcb-c: C6 backer on four layers with a solid In1 ground plane; planes stay in the DSN for the router (FR_PLANE_NETS); B15 plane probe experiment (c041c6e4)
tools: B15 routeflow profile on Freerouting 1.9.0 as the fallback behind the 2.4.1 run (238b8c2a)
tools: bench_report grades the Stage 4 gate per board and overall from the rows (0bfcbb2a)
tools: experiment finish as production (stub router, raw counts, re-finish from the kept session); pairs judged against the baseline; report from the latest row per key with recomputed verdicts (4d27578a)
tools: routeflow experiments run N configurations at once with their own lock and timeout scale; vast.ai setup and driver; S1 and A/B files for A21, B14, B15 and C6 (beaca2fa)
tools: 2.x fanout pre-pass off by default (FR_FANOUT), a fanout-on variant in the A/B (ab99ab55)
tools: routeflow profiles route on Freerouting 2.4.1; no -drc in the route command (2.4.1 makes it a DRC-only job) (2d24c9b0)
tools: FR_JAR drives Freerouting 2.4.1 beside 1.9.0 on the same DSN; the Stage 4 A/B experiments for A21, B15, C5, D7, E4 (d96a2537)
pcb-a: the pair report and the pair gate on PCB-A too (one USB pair over 1 mm on A21) (c740e5aa)
tools: routeflow routes with rules-file knobs and remedies opens with a via-cost change before more passes (cdf6e724)
tools: stub router routes on any set of copper layers (STUB_LAYERS); B15’s finish gives it In2 and In3 (f0193baf)
tools: quality pass in the B15 and A21 finishes (870a5936)
tools: the finishes run the DRC-gated quality pass after the clean-up (44634b3c)
tools: via_merge pass with counters; the record notes it finds no removable excursions on B14 (e194b763)
tools: routeflow experiment mode (rules-file knobs, resumable, journaled), bench_report, the S1 sweeps for D7 and E4 (06bc1707)
tools: straighten pass with its DRC-gated wrapper, the probe results (rules-file via costs are the lever), fr_rules and FR_RULES in the route (557395c5)
tools: the quality programme’s instruments: route_metrics, bench_compare, strip_route, bench_baseline, fr_probe; routeflow quality stage (d55171fa)
tools: join_adjacent_pins joins neighbouring same-net pads before the route (B15’s recurring opens); route_audit region crop (dcd7be12)
tools: routeflow, the fail-closed supervisor around the board chains and Freerouting, with its methodology audit (b8e02542)
tools: FR_TIMEOUT sets the Freerouting time limit per attempt (six-layer boards need more than 75 min) (911a2dfb)
tools: FR_POWER_LAYERS hands plane layers to Freerouting as power layers instead of board-wide keep-outs (7cd00575)
tools: route_audit.py, the audit image of a routed board with its open ends for the self-audit ruling (f8248da5)
render: the Peli 1450 scene from Peli’s 1451-931 bodies, the face plate and backer, the battery row, nine antennas, cables, rulers and the 44-view set (9d590412)
pcb-c: C6, the U-shaped backer board under the aluminium face plate: generators, footprints with body slots, the gate with the stack height rule, chain and finish (b4b2de3c)
cad: the 1450 face layout (panel1450.py) and the aluminium face plate model, DXF and marking (658e0e65)
case: 1450 wall templates (upright plate, nine bulkheads at Z 88) and the battery row model; B15 six-layer generators, gate and finish (d8a09b95)
cad: stack height map of the A21/B14/D7 stack on a 5 mm grid, from the scene (c3324770)
tools: stack height map from the render scene’s bounding boxes, for the C6 gate (3c98318a)
pcb-b: In1 is a solid ground plane (board-wide track keep-out, vias allowed); the B14 finish retitles before the export (0752fc9e)
tools: pair mismatch as a hard gate with automatic meanders and an audit image per pair; appendix 32.40 rulings (861a1391)
tools: meander on segments of any angle, split across segments, with a B14 length-matching runner (c6d52379)
tools: post-route trombone meander for the short leg of a pair (a9dae2c2)
pcb-b: B14 routed and finished, the M.2 WiFi P2P socket on the CM5 PCIe lane (09e69c67)
pcb-a: A21, PCB-A re-routed with the net classes applied: rail islands and bottom bands, boost feeds on In2 and B.Cu, 0.6 mm cell-node links, USB pairs 0.2/0.15 (743d2e31)
pcb-d: D7 routed and finished for the DMR858M V1.0 board (cc4b9b07)
pcb-d: D7 routed and finished for the DMR858M V1.0 board (6d1b1acc)
tools: continuation route for a routed board with a few opens, wired into the A21 finish (21854024)
pcb-a: the A gate checks pattern coverage and reads the rail widths back after the route (835dcecc)
pcb-d: D7 content checks in the gate; PANEL.md control path and I2C map; NXP SC16IS740 sheet filed (6035948c)
pcb-b: B14 routed and finished, the M.2 WiFi P2P socket on the CM5 PCIe lane (15f73f31)
pcb-d: D7 for the DMR858M V1.0 board: carrier detect and knob code read on a PCA9555 0x26, SC16IS740 UART bridge 0x48, mic divider 47k/1k, no jumpers or bench header; 38 mm spacers; docs (5238b16c)
pcb-b: PCIe intra-pair length report in the gate (post-route warning) (4834792a)
pcb-b: B14 generators: M.2 E-key socket on the CM5 PCIe lane for the AW7915-AED WiFi P2P card, its 3.3 V buck and monitor, the second east-wall site; docs (6e910fbc)
pcb-d: D6 routed and finished at the 0.14 mm rule (d16372a4)
pcb-a,pcb-d: A20 and D6 routed and finished (fix round) (acfab382)
pcb-a,pcb-d: A20 and D6 routed and finished on the laptop (c76a0059)
pcb-b: B13 routed and finished on the laptop (efea0add)
ecad: A20 and D6 generators (hub and dongle channels out, WM8960 codec on I2S, J_AB1 2x9, Q5 corrected), B13 chain fixes, 0.4 mm connector escapes, contract check extended (91e5d596)
pcb-b: B13 Compute Module 5 carrier: generators, receptacle and module footprints, CM5 research and vendor sheets, appendix 32.35 and 32.36 (56ca0186)
ecad: PCB-C C5 finished, the sealed face (0 hard, 0 unrouted, 272 vias); die-cut seal outlines as DXF; case template with the seal parts named (780c4b5e)
ecad: PCB-C C5 generators for the sealed face: keyed switch holes, underside lead lands and SMD connectors, seal bands and die-cut outlines, masked frame rings, panel sounder; seal parts research (45505f68)
ecad: A19 rerouted on locked fine-pitch escapes (0 open, 0 hard), B12, E4 and E5 finished on real-net planes (d7c3e648)
case: the two external cables defined from Glenair sheets, USB receptacle ordered in the round-hole style (388b7639)
module: RS PRO 245-556 heater mat under the cells, enclosure grown for it, research filed (1141a369)
release: float nest model; C4 schematic PDF with the APEM lock texts, BOM untouched (6240cf69)
case: SMA bulkheads on the end walls (sheets 3 and 4), float nest model, second expander map and heating pad rule (37ee6631)
case: connector plate on the back wall per the Peli drawing; protection board ruling, section 32.31 (4e307f24)
release: A19, B12, E4 and E5 deliverables, all 0 hard and 0 unrouted; battery module model (d5f046d5)
cad: battery module enclosure, lid and floor cradle in build123d (0a139d4b)
dock: strip 278 x 60, east end at X 118 to clear the battery module cradle (117f8aa6)
case: wall receptacle plate and 1:1 cut-out template, appendix 32.29 (08d9644c)
dock: block board nets per contact, trimmed courtyards, strip power lands moved; battery module research filed (5ad799f2)
ecad: dock block board E5 generator; dock schematic layout fixed (9fc79a5e)
release: PCB-B B12 routed clean (0 hard, 0 unrouted), no X1202, three rails from PCB-A, deliverable (61404fca)
ecad: dock strip E4 generators: 285 x 60 four-layer strip, ideal-diode entry, LT8705A tracker, module entry and block lands, seven float clamps (3f81a3ea)
tools: grid router takes its grid and node budget from the environment for long connections (dd39efa4)
ecad: land patterns for the A19 parts from the data sheets (TPS61288 RQQ, BQ25792 RQM, SMP-MAX receptacle, Mill-Max 9 A pin and target) (300f95d5)
ecad: A19 generators (charger, gauge, three rails, power control, pad switch, seven-port hub, blind-mate sites, dock block); B12 T-Beam header out of the panel corridor (20f82188)
ecad: B12 generators, no X1202, three rail inputs, ribbon carries the shutdown request and kill; appendix 32.24 (81f7999f)
release: A18 (dock holes 1.1 mm for the Preci-Dip 813 connector) and E3 (junction D-hole flat per the Amphenol 132170 drawing), C4 schematic with the switch part numbers, handoff rebuilt, A17 and E2 retired (9a0f37e5)
ecad: A18 dock drills for the Preci-Dip 813 pins, E3 junction D-hole per the Amphenol 132170 drawing, panel switch part numbers, vendor documents (8ffef238)
release: A17 and B11 deliverables, order and review sets rebuilt; A16 and B10 retired (60f3f295)
ecad: A17 hub supply, its decoupling and the PWR LED on the module-rail plane so the ribbon 5 V track stays out of the hub escapes (b7c49c46)
ecad: B11 region boxes for the SDR parts and the XIAO pigtail header; build guide and READMEs for A17/B11 (a76f45b2)
ecad: A17/B11 pre-route fixes (panel header placed, spare-net test points, header east of the ZigBee slots, boost region), appendix section 32, assembly guide and panel contract for the module rail (f93c3c06)
ecad: A17 module rail (F3 + TPS61089 boost from the cell node, EN from the X1202 5 V sense) and B11 (real X1202 envelope from the Geekworm DXF, stack 10 mm west, GPIO header north, VH module-rail input) (b8cef471)

Fixes

pcb-p: the board was designed to numbers the process does not make at its own copper weight (41a73474)
tools: the rail check crashed the gate at the moment it decided, and board E lost its best result (31976dbd)
pcb-d: the 3.3 V rail named a load on another net and its own source as a load (61f4a750)
pcb: thirty-eight rails across five boards were never declared, so three checks were blind to them (6552eb53)
pcb-e: board E’s two logic rails were never declared, so they were judged as signals (fa4eb1f3)
tools: the signal classifier reads its board from the board table, not from the directory (a2773447)
pcb-b: the PCIe receive lines had no AC coupling capacitor, required by the module’s own datasheet (0ceb6f13)
tools: a gate wrote no verdict at all on any host without PyYAML (0e2ea194)
rules: evidence freshness compares instants, not text (a verdict at 23:16 UTC read as older than an epoch of 00:35+02:00); the first computed numbers are 10.2 percent verified, 4.8 failed, 85 inconclusive, NOT_READY (884dc616)
chain: the placed-board DRC fails closed (it swallowed its own exit status and a five-hour route followed an UNMEASURED board) (195d6b0d)
b: the project file’s net classes come from the generator’s own table, and no class may sit below the board minimum (B shipped USB and DIFF100 at 0.10 against 0.127); class_floor.py gates it (51b09db1)
tools: a stub pass that closed nothing writes nothing (A35’s round two segfaulted filling and saving an unchanged board, and the finish refused the phase) (83caadb0)
e: the ground-via grid is off for E, measured: it costs E’s route (0 hard 2 open without it, 11 hard 4 open with it) where it pays on D (2bbc9772)
gate: the final gate refuses a folder that is not the phase the tree declares (all five cut folders predate the return rules and each passed by being judged against itself) (6079a469)
tools: the ground-via grid asks the DRC until it names no via of its own (one pass left 104 of C’s inside rule areas) (b2d7cc22)
gate: rule 1 counts every filled zone as a reference plane (the name-prefix list missed E’s In2 power pours: E10 read 18 nets over for tracks on solid copper); return_gaps fills first (05c83d34)
b: PLACE_COUPLE_GAP back to 2.4: on the production pass 2.6 lays 31 where 2.4 laid 35, and one arm cannot resolve a knob inside the pass’s own scatter (dd27c8c5)
agent: the clock on the template note (e9a85f5c)
agent: a B template’s pair pass is the board’s own first pass (pair_env plus pair_passes[0]); the five placement cycles ran without two declared knobs (a3177b7d)
tools: the plane-pad predictor refuses a pad with NOWHERE to go (no free via site within 1.5 mm, or a track keep-out over it), not a pad the route has not reached yet (A36’s placed board had 244 of those) (9f864204)
tools: return_via names which of its two site conditions refused a via’s candidates (2951b053)
agent: the cycle stamp is converted to the verdict clock’s form once (82405f34)
agent: the reviewer is handed only this cycle’s verdicts, never the loop’s own or an earlier cycle’s (tier 2b’s finding on the fourth live cycle) (ae22eb2b)
pair: every timed wrapper sits where its names exist; a rule proves the package’s module-level names resolve in import order without pcbnew (85936c90)
pair: the timed search wrappers belong to the search module; the first split left them past the geometry anchor and the package failed to import on the box (13b99655)
agent: the runner’s exit code is its verdict code; a FAIL over a complete row set is the rows’ business, not an incomplete cycle (13ea18e2)
gates: return_via reads the board’s minimum clearance (KiCad 9 has no GetDefault); return_report measures both rules per layer on a routed board (9859e3cd)
agent: the evidence cohort keys the tools by their tree content, not the commit they were checked out at (68656b9f)
agent: a cycle is complete or it is nothing (runner status, one row per arm), ILLEGAL is unmeasured, the verdict is the arms’ and the review a count, evidence scoped to its cohort, artefacts per cycle, the exit-status contract of a pass, no stale counts, six-type benchmark rows quarantined, the experiment lock a claim; eight rules skip on a code-only checkout (8fc0ea31)
gates: the final gate fails closed (a seven-board manifest, quote folders and open certification fail the set, unjudged is never PASS) with an executed truth table; drc.sh’s cost line runs; the ledger appends under a lock; a prediction of zero is a prediction; a Skip helper for artefacts a checkout lacks (bb957da4)
routeflow: A36 and B20 profiles come when their boards are re-finished; a board’s phase equals its newest profile’s (c0db0e7c)
a: the PA head keep-out stops short of the output caps’ ground pads, whose escapes it was refusing (ccc08ea2)
a: the PA head keep-out covers the pads’ own band, not the island margin where the caps’ ground escapes run (704656f3)
tools: finish.sh’s second prune pass lost its fi for one commit; every shell tool is parsed by the suite now (cbe00e9e)
a: A35: the PA rail head keeps the router off its island, and the finish prunes dead stitch vias a second time after the rail prune (A34’s two gate items) (5fb98ead)
cloud: the box setup installs scipy, without which dc_drop reads every rail UNRESOLVED (found on box 51119564) (13c9d1cd)
pcb-b: B19’s schematic regenerated on the column-banded page: 62 pins and 23 labels the seam had separated are connected again, netlist identical to the 14 Sep one on every net and node line, ERC gate PASS (183e9d1d)
pcb-b: the three fan PWM pull-ups R151, R251, R351 are back: a stock note appended on 14 Sep had swallowed their call; a rule refuses a comment carrying a call (fbcc9c4b)
tools: the banded schematic page bands by the part’s column, never by an item’s own coordinate: B19’s wide symbols lost their labels across the seam (4e5aa294)
tools: the box clone is full depth; a shallow clone left every driver waiting for a hash it could not name (15 Sep 2026, box 51119564) (be97cad4)
release: the fab notes of C17, D11, E9 and P4 read their impedance line off the board’s own class: C and E declare no target, D’s pairs are 0.3 mm / 0.2 mm (3c2a669a)
tools: export_jlc’s impedance line closes its parenthesis; the previous commit did not export at all (4524b9d1)
tools: the fab note’s impedance line comes from the board’s own USB class and its declared target; C17 asked the fab to tune pairs that declare none, and 0.2/0.15 was a constant (40175812)
sch: the six schematics regenerated on pages that hold them (A 2074 x 1230 mm in two bands, B 2074 x 1710); every netlist identical to the committed one apart from its source path (2a9543ac)
sch: the schematic page holds the drawing: the row of columns is folded into bands under a user page, so the PDF is no longer an empty A0 frame (A’s drawing was 2.8 m wide, B’s 3.9 m) (92d0cddf)
a: the VBUS20 leg keep-out leaves a band round every foreign pad row inside the leg, so the fanout keeps its stubs (1e9d8674)
a: the VBUS20 leg keep-out is shortened at the end nearer R16, decided by distance (85d6bb63)
a: the VBUS20 leg keep-out stops 2.5 mm short of R16, whose sense escapes leave along that edge (f77d205a)
tools: the A33 profile’s clean flag is its own; validate 20 of 20 (81fa2f5c)
tools: the A33 profile’s finish cuts A33 (9be3a7f7)
tools: the router launcher dismisses a modal warning Freerouting holds for a click; B19 sat three hours on ’normalization of net failed’ under Xvfb (61b4393a)
tools: rail_prune reads every piece before the first connectivity build (the wrappers go stale after it); A32: 327 router pieces off twelve rails, VBAT 124 of them (1ee468ca)
tools: rail_prune judges tracks and vias only; an arc has no start and end to put back (2cb3acf9)
tools: a stub closure is no wider than the track end it joins and takes the board’s minimum via under 0.25 mm; A32’s last open asked a 0.5 mm class track through a QFN’s escape field (4c14580b)
tools: B’s profiles expect the one gate line their board declares; a profile’s gate count is its board’s declaration, by rule (c2f95a35)
c: the backer legend carried a literal C7 and the final gate refused C17’s folder for it; the phase reaches the silk only through the chain; the public rows and the order row name C17 (f72d6742)
tools: a measurement writes an advisory verdict the supervisor does not read as the stage’s; the pair-copper DRC before the prune and a declared-off predictor are measurements (ea082006)
c: a hole is not a BOM line: the two camera holes leave the BOM, kisch.part carries in_bom (5e5bf2b1)
tools: a stub router with nothing to close leaves before pcbnew’s teardown can crash it; C17’s second re-finish died there at exit 139 (97e84ca0)
c: C17 routed to 0 hard and 0 unrouted with the test points beside their nets; the sounder, the headset jacks and the camera holes declared, the EMCON buffer’s code read back (3d6d844f)
tools: MISSING is a list; the previous commit called update on it and three contract fixtures failed (6dd67510)
tools: an empty pin map is a missing board, and B runs no gate on its mechanical board (7ff45584)
pcb-b: a board that declares a coupled fraction is judged on the routed board by length, not held on a count; B19 routes twelve passes (7b9678f2)
pcb-c: the test-point columns clear the switches’ courtyards, which run 2.3 mm past their cut-outs (38709642)
pcb-c: the two e-paper test points are in one region list, not two (1a5e6d11)
pcb-c: the test points join FIXED before the loop that places it, so the region lists skip them (5cf4e6cc)
pcb-c: the test points are placed by the one FIXED loop, not twice (5d9ee8ca)
pcb-a: A32 closes the three gaps A30’s route bridged with 0.5 mm inner tracks (f39f222c)
tools: a track goal in the stub router is the track’s own copper, not a disc around the DRC’s point (fe5760cc)
pcb-a: the slot island keep-out stops at the finger’s foot (d5a3bb9d)
routeflow: a worse round is not finished, and every exit restores and finishes the best board (fef26cd3)
pcb-a: the VBAT slot islands’ via columns carry a track keep-out (00188ff8)
pcb-c: the committed C profiles pin the clone, not the scratch tree a driver built (3528d1d1)
tools: the closure ladder gets a wall-clock budget, because every shape costs a board DRC (14573b5f)
tools: the stub router writes unbuffered, so a search that is cut leaves its line (575ea76a)
pcb-a: the HF head island is the capacitor column, not the bounding box of four scattered pads (d1b63449)
tools: the cross-board contracts read the declared phase directory, not the newest arm (a9be3216)
pcb-a: no keep-out on the VBUS20 island, and the two attempts at one are why (888d9e6c)
pcb-a: the gap between two of these capacitors is the next one’s ground pad (876c59b0)
pcb-a: the VBUS20 keep-out is the pad row’s band, not the island’s outer margin (3af804bc)
pcb-a: the VBAT hand-over vias find their own clear stretch of the trunk (7a213283)
pcb-a: A29, four rails measured on A28’s own copper and every one is a layer transition (26eeda25)
order: a maker and a part number inside parentheses name the part (c09f11a5)
tools: a via and a track end at one point are one point, with one layer set (44b8499d)
tools: an island pair is named as it is tried, and the refusal list is no longer cut at fourteen (07a474fb)
tools: a closure is searched at the clearance the net’s class asks for (2c28b731)
tools: a closure is tried on every layer its two anchors share (d9139460)
pcb-b: the pair’s own two tracks at a layer change are a fold test, not a clearance test (776f5b8c)
tools: every trial board of a closure is built in its own process (7ad6dd1d)
tools: a refused closure is offered the other pairs of the same two islands (5e06e16d)
pcb-a: the length matcher is offered the pair’s locked copper alongside its unlocked pieces (04f03caf)
pcb-b: the pair’s layer change is judged against its partner before it is laid (5644d93f)
order: a bare board has no BOM, so it cannot have a BOM status (f9afbe43)
tests: the leg-match rules read the equaliser’s whole body and its local side test (b906c8e9)
pcb-a: the bump’s side is the nearest partner piece, not the partner’s centroid (879940c8)
pcb-a: the leg match measures the whole net, tries smaller bumps and names what refused them (e400503e)
pcb-a: the leg equaliser takes the pair’s net objects, not its names (ccbc590b)
tools: a pair laid end to end by the pre-router has no unlocked copper, so the length gate is given its locked copper (22cc6adc)
tools: the final gate takes its stem from the gerber zip and is declared a reader on the pin (32275c4b)
order: a class row stays unanswered whatever an allow list says, and B’s phase copy carries its board’s declaration (1bfc361b)
order: the certification reads the boards’ own allow lists too: 513 of 517 rows settled (34571171)
pcb-b: the controllers’ SWD lands are declared: copper on our own board, no part fitted (8b2e80d8)
pcb-b: the three fan connectors carry the JST part the schematic names (6abb4120)
tools: the meander ladder goes down to a quarter of a millimetre, where A’s free space is (daed7710)
pcb-c: the stub router gets a window that can hold C’s last connection (58c88b9a)
pcb-c: the continuation’s ceiling comes from C’s measured pass rate, not from 80 passes in 900 seconds (6d288fc4)
tools: direct_close measured a trial board at KiCad’s unconnected cap, and the finish never saw it crash (0b38cf05)
pcb-a: the VBAT comb walks round the charger’s via column instead of being cut by it (e4564a3f)
pcb-e: the VIN_RAW In2 pour takes the empty strip north of its own via heads (c007c247)
tools: an island gets six candidate spots before it is left open, which is E8’s last connection (4b33e029)
ecad: the finish refills before the gate and the rail checks: E8’s CELL_F reads MET on the board it is cutting (9619f425)
gates: a supplementary ground pour on a routing layer is not judged by its coverage (e29f4580)
tools: stitch_prune refuses an unfilled board, where every via reads as abandoned (2c1e49a3)
pcb-b: the pair’s end emissions are asked about the partner before they are laid, and the approach moves when the last hop is the violation (583bd88b)
pcb-a: A26 power copper: the PA band reaches its shunt, VIN_RAW’s head gets its second layer, VBUS20 leaves VBAT’s trunk, the HF run steps round J_AB2 (f3e9e4ac)
tools: an option a usage line offers must be read; dc_drop draws the picture it has promised since 8 September (8402c3a1)
ecad: the stub stage must not leave a board more open than it found it (6e0dcd54)
ecad: a netlist older than its schematic describes a board that no longer exists (c99cd183)
ecad: the barrel ratio is reported, not gated, because it does not converge (4cd6efd8)
ecad: two barrels per source track on P3, six per FET (50a335b7)
ecad: E7’s source pad takes ten barrels, not six (edbe4b98)
ecad: P3’s vias go where the crossing is, in the FET’s own source tracks (a5c74be8)
ecad: P3’s two failing bands give up the second layer, because the crossing was the problem (376e78bb)
ecad: P3’s bands go to 3.6 mm so either layer can carry the rail (b61f45e3)
ecad: IOCA grows north, not west, and the two rails get what they still needed (d77947d2)
ecad: D’s band reaches C7’s pad instead of stopping short of it (35dc4f82)
ecad: the board files declare A25 and C11, which their new profiles cut (98e4a95a)
ecad: B’s ground return is not always at the part that supplies it (e5ef7b9f)
ecad: D’s rail trunk went through J_HARN1’s pin field (e59d6491)
ecad: a via tangent to the copper it joins is not joined to it (de64970a)
ecad: P3’s layer crossing happens at one end, so the vias go three across at 1.0 mm (0238ffe2)
ecad: E7’s block lands each had one 0.4 mm via for 2 A, and its source pad had no copper on its own layer (d9613db4)
ecad: P3’s stitch vias go across the band, not only along it (73af8e51)
ecad: P3’s barrels were the neck and nothing had ever judged them (5e55bf36)
ecad: the stackup reader wanted one line per layer and KiCad 9 writes five (75327b69)
ecad: the via rule asserts the property, not the spelling it was written against (bf0e8f43)
ecad: the via pass read dT before the loop assigns it (9b361dcc)
ecad: VBUS20’s island was cut and the current found an inner track; the HF island squeezed its own gate drive (e572c4ba)
ecad: the USB net class was built on C, D and E and never registered, inside a comment (67e375c6)
ecad: board B’s BOM, 44 uncoded lines answered and two defects behind them (eb7cb700)
ecad: E7’s source pad gets a second row of power vias (56856155)
ecad: the first VBUS20 copper bought two hard items and no current (729f12a0)
ecad: board A’s placement generator could not run, and nothing said so until a chain tried (18fcf43a)
ecad: P3’s pack current enters its band through three 0.6 mm tracks; decision 23 puts a number in front of ruling 9 (3a1f36b5)
ecad: a rail’s source is the power path, not the part that controls it (27625ab6)
ecad: a cell a pour fills is full copper, and a track inside its own pour is not a lone conductor (e014e7c4)
ecad: clamp a conductor to the current its rail is given, refuse only the gross excess (08716531)
ecad: the conductor current was a potential difference across a path the conductance did not describe (70dbd5cb)
ecad: every rail names where its current goes, and a rail without loads is refused at declaration (2f8d2194)
tools: tier 2b caught a fix that was written and never applied, and two more (77e1c66a)
tools: a rail whose loads are undeclared is not judged, and that is half the density failures (cbaedc77)
ecad: the import note leaves the project folder, which must match what was proved (eaac2378)
order: a manufacturer’s prefix is the same part, and every LED row carries a code (589012fc)
tools: the current-density bar is lenient, not strict, and twelve rails exceed it (a69923f0)
tools: the stub router’s class lookup was dead twice over (625657a7)
tools: straighten normalises the net class once, and the map is off limits (f318aa0c)
tools: which class a net is in, answered once; two readers had it wrong (63f88a7d)
order: the fab note reads the copper weight and the stackup off the board (e2abc204)
tools: a routeflow run whose tools and board come from different trees is refused (017ed911)
tests: the new packer knob is registered, and the rule that guards it says what it guards (02cb0888)
place: B’s PoE inlet is placed, not packed, and seven violations go with it (0a8720a1)
place: board B’s region overflow is ZERO, owner ruling 13 (a9f32294)
place: eleven of board B’s twelve regions are sized, and the instrument had a third defect (c7c7ebe3)
place: nine of board B’s twelve overflowing regions are sized, owner ruling 13 (b00e6b81)
e5: the dock block’s board carries a stackup, and it is the 2 oz one (efe5a766)
p: a finish declaration that the finish cannot see switches nothing on (4d763177)
order: A’s SMA rows named the device at the far end of the pigtail (fd6a1b3d)
order: owner ruling 10’s own fill rule could never fire (eb22bddf)
p: board P declares the stitch pruner, with the via it removes measured (5fa22871)
escape: solder paste is not copper, and it was refusing every thermal via (620215b1)
order: the panel and dock parts nobody had written a purchase route for (c3d5cd9f)
order: a socket on the board is not the lead that plugs into it (ab3e57d5)
place: a region that cannot hold its parts blocks instead of warning (fee95436)
order: the shelf packer walks over the parts that are already there (7727faca)
order: every connector land that JLCPCB stocks names its own part (07c57b30)
placement: a through-hole collision is named, not stepped around, and decision 11 (36f3bbbd)
pipeline: the red team’s route-supervisor and artefact findings (be767218)
agent: the red team’s experiment-integrity findings, all of them (9c10e466)
placement: the shelf packer had no obstacle awareness, and a band is not an obstacle (e097d591)
repo: the build VM’s hostname was in four public files (003f4c25)
escape: the exposed-pad thermal vias laid copper without asking anything (661cce63)
prefanout: a margin against the board must be the board’s own (43087cc9)
escape: a nearness window measured from a pad’s centre misses a pad that is wide (f63dfec5)
footprints: both TI mux lands read a centreline dimension as an overall one (a0d1ecec)
docs: the layer verdict was KEEP and read as endorsement; it is NOT_FREED (e2657c22)
tools: the runner is the judge and there is only one (fe9e62e9)
tools: a knob this run cannot execute is refused like a knob nobody reads (e23c4873)
tools: the five findings tier 2b made against the legality change (e78fb77d)
tools: the pair count alone is a gameable objective, and a flag is not a threshold (58362e32)
tools: the seven findings tier 2b made against the change that introduced it (145eb4ed)
preroute: the refusal position carries no parentheses, which would have cut the reason in half (e29783f2)
handoff: the order notes name the phases the tree actually ships (a2893ea7)
parts: A24’s remaining codes, and the eFuse ILM resistors get a resistance (1f1a180a)
intent: CELL+ declares its load, and the rail goes from 2.21 percent to 0.08 (7ded3485)
tools: the stub router takes its connectivity count lazily (42b28b83)
tools: the straightener leaves the nets of a differential pair class alone (6d27a56e)
tools: a meander is locked copper (bdacfddf)
tools: a via standing in a pad of its own net is not dangling (754417c7)
tools: the legend pass stamps the phase the finish was given (d5c651d4)
tools: the phase comes from the board file and full.sh exports it (d2335289)
tools: the stub router reads its plane nets from the board, not from a hard-coded string (23509ecb)
tools: the legend pass no longer writes a stale phase and a stale stackup onto the silk (1af19618)
preroute: PAIR_END_STRICT judges the copper laid WITHOUT asking a map, not the map (c5d24792)
tools: the stub router checks that a closure closed anything, and takes it off when it did not (0b347488)
tools: direct_close anchors to the piece the DRC named, not the nearest copper to its position (0316d886)
tools: direct_close works on the pair the DRC named, at the positions it named (5f27a3a3)
tools: the DRC refuses a board whose project file is not beside it (fbe4ae05)
tools: the pair report reads the whole-pair refusals, and prints what it still cannot read (f0bd2365)
tools: the continuation route gets the plane treatment its own route was given (ece214be)
tools: one shell-side answer to which Freerouting jar runs, and the per-pass session on every capped run (c02880ff)
tools: C’s continuation route runs up to 15 opens, which is the case it was written for (918d609f)
chain: a board the pair gate refuses gets its DRC before the block, and the entry guard is worth plus one (5330fb42)
preroute: the via diameter helper cannot raise out of a diagnostic (ac0405b7)
route: correct the note, C10’s router was alive; the display race stands on its own (bfefb918)
route: the last two routers take a named display, and the rule reads code rather than comments (48945bc4)
route: every router takes a named display, and no script kills every Xvfb on the host (c962acae)
gen-a: the charger’s switching capacitors are placed at their inductor, not by the packer (20a13c0b)
gen-a: FES moves up so CHQ keeps its height and its capacitors stay off the inductor (d8609760)
gen-a: the ESD at 90 degrees lays A’s third pair, J_AB2 into a clear window, CHQ off the inductor (205bd0b6)
tests: the window the entry rule reads covers the comment that explains it (927b5f2e)
tests: the entry-region rule follows the shape it guards (81d49f34)
preroute: a blocked cell in the entry region is put to the geometry before the pair is refused (fb75db94)
preroute: a skip parameter landed in the helper above the one it was meant for (55cc3857)
gen-a: the wall port’s ESD sits at its connector, not 86 mm away (9e7420e0)
preroute,gen-a: a via is measured with its layer; J_AB2 turned round to untwist the wall pair (a2ea43b1)
gen-a: J_AB2 into a window the rod-nut gate accepts (0096188e)
gen-a: one source for the IDC land, so J_MEZZ1 stops carrying the stock pads (a83f2cd3)
preroute: the entry exemption asks the pads-only map, and appendix 32.135 (694bd737)
preroute: the cross-net test names the counterparty and leaves the verdict to the DRC (1971a2f2)
preroute: the cross-net gate exempts the pair’s own two nets (3a8dfc66)
gen-a: two placement regions overlapped and put the charger FETs under the front end’s resistors (f4dabf0d)
preroute: the trim takes only pieces wholly inside its radius (618438cc)
preroute: a fan’s own pad field is a map that exempts pads and no track (1a08bb7e)
preroute: a fan’s last 1.2 mm is excused only where the pair’s own pad is, and the dive’s fan is judged like any other (458781e4)
preroute: the own-copper test uses the fold bar, and each of the four guards has a knob (88df4a15)
preroute: a twist is declared only where the pads really are on opposite sides (8d61fed6)
preroute: the own-legs gate judges each layer by its own width and each via by its own radius (6e14055f)
preroute: the merged polyline is judged for the fold merging can create (a1353cac)
preroute: the mutual leg test is a fold detector, not a second clearance test (B19 22 of 48 against 9) (4ec8cbbd)
ecad: the narrow-pad IDC lands are in the library and declared by the boards that use them (3e9c25d4)
preroute: the dive’s N fan and the direct legs are judged against the partner’s copper (e353f6a6)
preroute: the two offset legs of a pair judged against each other; the IDC land is a per-board measurement (2ab96992)
preroute: a pair may not short its own partner: the fan and the sub-cell stub ask before they lay (09648409)
tools: a blocked LCSC code can be wrong on one land and right on another (0df1b164)
pre-router: the station swap crosses the hub side by construction, measured (030259d8)
docs: every section from 32.118 on carried tomorrow’s date (40912fbd)
a: A’s schematic regenerated for the harness pin map, and the contract passes again (3685f0f6)
docs: the B19 arm counted the tool’s own SWAP and DIVE lines as failures (0307a645)
tools: a footprint’s origin is pin 1, and the pre-router read it as a centre (44a756a1)
a,d: a pair cannot leave an inner row of a 2.54 mm IDC header, measured (926fd41b)
tools: the deliverable gate could not see the declaration the project actually uses (57da0494)
tools: the stitch pruner is declared per board and off everywhere (d974d581)
tools: three from a review of the board-mutating tools (879f4249)
routeflow: a restored best board gets its finish, or it is only half kept (83c059f7)
e: the phase copy carried a stale allow list, and that is what refused a clean E (89bacf2b)
tools: the stitch pruner was judged against zero, so it could never help a board that was not already clean (88bae624)
routeflow: keep the best routed board of a run, because a remedy can make one worse (0f1611b1)
tools: the stub router emitted a straight run as one segment per two cells, and that is what refused E (9a85427f)
routeflow: the journal and the provenance named the stock jar while the patched one ran (2a5f5718)
routeflow: every profile pinned the STOCK jar, which bypassed the refusal added for exactly that (16644dbd)
tools: stitch_prune had its safety test the wrong way round (1c6448d2)
e: the allow line for E’s sensor headers matched nothing, and a dead allow line is named now (3ca3ee73)
tools: a code is wrong FOR A PART, not in general, and the rejection was keyed on the code alone (82ba4a63)
tools: P3’s three pack connectors get their LCSC codes, and a round starts with a clean verdict channel (d7377806)
routeflow: the horizon was computed and never passed to the collector (f304c7a7)
verdict: one clock, because the horizon was comparing local time against UTC and excluded nothing (574ae612)
routeflow: a stage is judged only by the verdicts it wrote (aa87f38e)
tools: a board missing from the tree is an inconclusive contract set, not eleven broken contracts (0319eca0)
routeflow: correction, the generator-log rule did not fire on the profile it was written for (e42db308)
routeflow: c7 and c8 declared a generator log no chain writes, and validate now checks that (6bab497c)
tools: hardset’s verdict honours the stage it was always given, so a pre-route board stops failing for being unrouted (f0e8efd4)
routeflow: the router lock refusal names the knob that lifts it (374a2c93)
tools: three from a review: an escaped quote ended a parse, a resolve ran twice, a stop named a log nobody would read (0f608207)
tests: test_finish_order used sys.executable without importing sys (966d2643)
tools: netlist_board read KiCad’s unconnected-pin placeholder as a net and blocked B19 (ad1c6a60)
tools: the order set describes the board it ships: make_handoff resolves the phase from the tree (ca9d733c)
tools: the finish dispatch runs from the ecad directory, and a rule says so (44aff049)
route: the stock-jar fallback is a decision now, not a silence (93c4e61b)
preroute: the leg test gets its own knob, so an arm stays one variable (85ebe300)
preroute: an entry-station end whose legs cannot leave it is not an end (f788910f)
preroute: the corridor end-chooser tests the legs, not only the stubs (40d1bf19)
straighten: a work budget, because it is quadratic and it stopped a finish for an hour (71c31239)
impedance: a declared zero is a pass, an undeclared zero is inconclusive (379de5ed)
preroute: refuse a board whose pair classes cannot be read; test the corridor end where the stub starts (d9e4c2e5)
preroute: the map mode joins the counter that already existed, rather than a second one (32c5ff84)
tools: a random UUID decided which escapes fit; the laying passes have a stable order now (bf5a2395)
tools: the placed snapshot is written for every board, not only the ones with pairs (63c9527d)
tools: the last unbounded wait, and the stale B5 board that any glob picked first (6c5b4ba8)
parts: the VBAT bulk and the 145 MHz filter inductors, both unbuildable as drawn (559c8592)
generators: a comment must not swallow the calls after it, now a gate (62960469)
gates: three gates that could not fire, and the BOM blanks fall from 320 to 23 (fa4c5e85)
parts: two Coilcraft part numbers that do not exist, and the jellybean search that hid them (f9d65d40)
parts: eight wrong LCSC codes in shipped BOMs, found by the certifier reading each row’s own text (e0f3ef4f)
tools: the coverage scan read only the schematic generators, and four real parts were named elsewhere (c095abdd)
tools: the deliverable DRC histogram has never printed, its pattern was a grep error (f7bf0e59)
tools: no silent fallbacks in the pre-router, an exact heuristic, and the chain carries the pair configuration (fa3cbbfe)
tools: the hard set is one set in the shell too, and a broken attempt can no longer read as a routing failure (f4c754e6)
tools: close the fix-propagation matrix across the six finishes (7d8eb959)
tools: the stripline comparison was two different geometries, and the record’s 74 ohm finding falls with it (eaa3e2f6)
tools: the DRC report is an output, not a file that happens to be there (9768cd5b)
tools: every finish’s wait has a deadline and refuses rather than waiting forever (0bfba73c)
tools: the pre-router’s re-exec is for the script, never for an importer (6858e524)
tools: dc_drop says what it does, prints the budget it used, and refuses a mesh it did not solve (f19cdd4e)
tools: the rasterisation cache belongs to its grid, and the adaptive grid refuses to run under a negotiated plan (fc75809a)
ecad: the six schematic generators share one engine and ic() is strict on every board again (60d9e098)
tools: the P board shares the engine’s part list from the first part, not from halfway down (15c0c6ab)
tools: regrade the benchmark by board and mark every six-type verdict; the negotiator returns what the laying pass did (802f8a30)
tools: one hard set for every gate, the baseline keyed by board, failure propagated, preflight before the spend (7baedd89)
tools: the negotiator keeps the least contested plan, not the one with the most corridors (d4693ccc)
tools: a negotiated corridor owns its ends, the laying pass does not re-choose them (56265c1d)
tools: the negotiator counts its sections and says what it planned (e7f6aaab)
ecad: B’s fine-pitch margin goes back to 1.6, measured against the corrected corridor slack (e3a7af64)
tools: A’s placement gets the new spare-line test point (39a0a55e)
tools: a pair whose legs cross gets the escape-via second chance, like a failed section (edd1c604)
tools: the pre-router’s corridor slack is 0.12 mm, measured: 38 of 113 pairs at 0.25, 49 at 0.12 (67dd214d)
ecad: B’s fine-pitch escape margin is 2.6 mm, measured: 194 pads with no escape at 1.6, 69 at 2.6 (b33d8b6f)
tools: the B placement gives the wide escape margin only to the QFN and QFP rows, as C and E already do (0d5f27eb)
tools: every chain with a pre-router keeps the placed board before it (388c1f67)
tools: rip-up is off by default: measured, it lays 224 times and ends with 29 of 113 against the greedy pass’s 38 (fee28f10)
tools: a station walled in along the P to N normal falls back to the sweep instead of returning a blocked corridor end (f3db3fd6)
tools: the escape-via entry is a per-pair fallback, not a mode: it gains 27 pairs on B19 and costs D10 two (81bbd290)
tools: pour coverage, use the KiCad 9 intersection call so the board clip actually applies (70b6d93f)
tools: pour coverage is measured against the outline inside the board, not the drawn rectangle (5df349c7)
ecad: the spare ribbon line keeps a test point on A and none on B, where it no longer lands (9d643ea5)
ecad: every ribbon differential pair sits in one column of its header, ground pins on both sides (8bc3a0e1)
tools: the B chain keeps the placed board before the pre-router, the input every pre-router measurement needs (85344c7d)
tools: pre-router: a corridor end must be a cell both legs can still reach their pads from (a7222f10)
tools: pre-router: strip a station’s escape by following the chain out of the pad, not by a 3 mm radius (977997f5)
tools: pre-router: cut the self-intersections out of an offset leg, which is what made the two legs of nine B19 pairs cross (d5da2078)
tools: partition stage two, sequential mode: the merged board is stage1, and a stale session or log of a previous pass is cleared (a6d41c4c)
tools: the partition reconcile judges the stub router’s closures like every other finish does (610ef820)
tools: calibrate the pair expansion budget, and the mitre change is measured as neutral (5769e87f)
tools: a right-angle corner takes the arc, not the mitre, in the pair legs (be43f81e)
tools: the pair budget is counted in expansions, because a clock made the pass non-reproducible (d8493868)
tools: stub_accept refuses a closure that costs more copper than the net is worth (2ccb7fc6)
tools: the stub router no longer asks a pad for a polygon on a layer it is not on (376602e6)
pcb-b: the voted logic takes the QMX bay’s underside instead of crowding the controller pockets (4fbd0324)
pcb-b: R500 was listed twice when the voted logic was split three ways (0dd7b15c)
pcb-b: the placement predictor went from one collision to twenty three, and the cause was mine (2e208fba)
tools: the pair pre-router reports each pair as it happens, not only when the pass ends (1bea879e)
tools: the B19 chain runs the pair pre-router with a 300 second budget per pair (7efd252b)
sch: A22’s device rail is declared at the current B16 now draws from it (793ea7fd)
sch: a bank now outlives its module: hub, both host selects and the hub core leave the slot rail (b22524e4)
ecad: three controller pockets instead of one band, both ends of each CAN fabric terminated, the gate follows the ring (280a3a1d)
ecad: the two host-select muxes get their TI land patterns and the TMUXHS4212 its missing ground pins (ab0e12f2)
tools: the deliverable gate stops reading a board’s own name as a stale phase, and bare lands as missing from the CPL (ae6ec69c)
sch: the fabric’s capacitors clear the SIM blocks at C86 to C91; the generator builds and the ring reads back correct (612860f0)
sch: the four USB bridges leave the slot rails, three floating FET gates get their pull-downs, the panel controller is on slot 1’s hub (096b67cc)
tools: the body notch is only as deep as the window needs, and the notch test reads the courtyard, not the silk (c2333029)
sch: the E comment goes on its own line, it had swallowed TP13 and two pull-ups; C becomes C10 for the recessed face (44e2e2c2)
cad: the monitor sits IN the plate with its glass level with the aluminium, per the standing ruling; a gate for proud display surfaces (ad3b00c2)
tools: D defined pour() twice and the live one never removed pour islands; P had no island removal at all (e55113ea)
cad: the face re-spaced around the Xenarc, which is 19 mm taller than the display it replaced; a gate for two things on the plate (6c489fc6)
tools: a corridor keeps its own ends free of the behind-station mask and starts from an open block, not the first pocket that fits (e6d5d859)
sch: E’s Geiger series resistor is in the path it was drawn for; contract 16 refuses an in-line part that is in line with nothing (0fa39ec7)
tools: the dense fanout sample tests tracks only, not the pad lane; a D placement candidate can be swept from the environment (fd096e65)
tools: the pre-router never leaves its two legs crossing; the stagger rule applies to pad rows, not to two-pad passives; appendix 32.83 (ec7eca1b)
tools: the fanout stub is sampled every 0.2 mm, not at two points; a stub’s A* frees a disc at both ends, which are its own net’s copper (9d9eac15)
tools: the escape stagger never lands on the router’s own limit; the pairs claim copper before the fanout; pour_stitch armed in every finish (0eb5d108)
tools: restore gen_sch_d.py, my rail-note edit had cut 350 lines out of it; the 3 percent budget is one line now (5c243a68)
tools: repair the D rail note, and the E dock’s only pair is a full-speed link with no impedance target (ba9df2ca)
tools: the D hub’s port 3 resistors move 1.5 mm east; the 3.6 mm hop from U4 pin 19 had no path on any layer (04477d3d)
tools: the D mezzanine rail carries the budget its loads need, 3 percent, with the load list as the reason (9e61ee3f)
tools: the escape-fan box was only ever the inflate, so the protection never ran; built from the courtyard edges now (c18d936b)
tools: the second decoupling pass keeps out of escape fans; measured as the cause of the lost escapes, not the reservation (299fd363)
tools: the fan a reserved slot must avoid belongs to every escaped IC, not only 0.4 mm parts (26825060)
tools: a reserved decoupling slot never sits in a fine-pitch part’s escape fan, and the block imports its own os (0e2570f7)
tools: the new EMCON pull-downs get a place beside the gates they protect (c7efd6e5)
hw: EMCON has one driver and one sense, low silences everywhere, and a missing panel inhibits; the PoE feed loses its 24.9 ohm series resistor (5d9efaf7)
release: the 23 wrong LCSC codes reach the deliverable BOMs; verify_deliverable refuses a blocked code from now on (dd7fcda2)
tools: the pair pre-router reads footprint-local keep-outs; it was laying pairs straight through them (9a9b2ba8)
tools: a net class clearance below the board minimum is refused; it cost A23 twenty five clearance violations between pair legs (4ffa0b66)
tools: two laid runs crossing is left on the board for the gate, never resolved by deleting half a pre-routed pair (46031524)
tools: prune the escape, never the pre-routed pair leg; among the locked items in a violation take the shortest (53b899c0)
tools: the sounder driver column sits in the measured 6.2 mm gap between the sounder and the jack courtyards (77a003e2)
tools: the sounder driver column clears the sounder’s own solder lands as well as the jack (01f13e3a)
tools: an escape that shorts its own part’s neighbouring pad is the escape geometry, not the placement; counted on its own line (e3685edf)
tools: the sounder driver column sits clear of the jack hole and the sounder keep-out (f7ffb88f)
tools: the sounder driver sits at the sounder; on C8 it was 294 mm away and BZ_K was the one net nothing could close (84e9ff62)
routeflow: B17’s pass ceiling comes from B16’s measured curve, 16 passes in a seven hour budget, not 100 (42f094b5)
tools: the in-pad fanout via holds its clearance to existing tracks, not only to pads and vias (0e5c1ad1)
tools: a pair’s last fan into its pads is tested and routed, not laid blind over other nets’ escapes (319f3b3a)
tools: a pruned escape blocks the chain only when another part’s pad caused it; the C panel USB link is full speed and declares no impedance target (72019735)
tools: the C panel rail carries the budget its loads actually need, 5 percent, with the reason in the intent (d6ff9aa1)
tools: no straight tail run into a 0.4 mm row station; its escape vias are the section’s ends, as the corridor predicate already said (609f672b)
tools: the pair debug print applies the same station exemption as the check it explains, and names the run and the distance (5d64df71)
routeflow: A23’s pass ceiling comes from a measured pass rate, 18 passes in a five hour budget; 120 could never finish and cost two rounds (aefac2fb)
tools: escape_prune names the violation and the counterparty for every pad it strips; the same-depth pair escape is withdrawn on measurement; the P board declares its three gauge supply pins (a558b24e)
tools: declare the six PTT and EMCON gate bypass capacitors on the D board; correct the record that said they were absent (2268cefa)
tools: a differential pair’s two pads share their escape depth, so the pair leaves the row together; alternating depths left 0.6 mm where a 100 ohm pair needs 0.65 (b224aeab)
tools: the panel board gets three hours for its thirty passes, which at 4.5 minutes a pass do not fit in ninety minutes (2dc38848)
tools: the panel board routes 30 passes, not 100; at 4.5 minutes a pass it could never reach its ceiling and a session is only written when the job ends (e9a97639)
tools: the pair pre-router follows the same row rule as the escape pass, so a leg into a card socket ends at the escape via instead of aiming at a pad behind a wall of them (8ee4e205)
tools: a solder jumper is copper, not a part JLC places, so it joins the bench prefixes of the deliverable check (22306c43)
tools: the board gate honours bypass-allow.txt too, so a recorded decoupling exception does not fail every board silently twice (55402f59)
tools: the pad-to-plane pass refills and re-reads the board first, so it sees the items it exists for (2e11a852)
tools: withdraw the per-class layer rule, measured: C8 never finished a pass with it and auto-routed in 14 minutes without it, and the router does not honour it anyway (6741c56b)
tools: repair escape.py, a comment landed inside the attempt-list expression and broke the file (37d584fc)
tools: the depth stagger fires only where it has clearance margin; at 0.4 mm with a 0.45 via it left 0.075 mm and put four violations on A23’s charger (c2cb0b61)
tools: the fine escape scheme takes a 0.5 mm part only when its row is long; on every short one it put the vias 0.075 mm from their neighbours (9cf7618a)
tools: A23’s dock copper keeps its track keep-out off the header’s escape area, which is why two routes ran to their limit without a session; the 0.5 mm rows take the proven fine-pitch escape scheme by pitch instead of by a hard-coded reference (c7501e2d)
tools: the pad-to-plane closure accepts one via at a time, so a good closure is not thrown away with a bad one (981c0494)
tools: D9’s port-4 terminations north-east of the hub on the front, clear of its courtyard and the pull-down column (dbe587bb)
tools: D9’s unused hub port terminations sit at the pins instead of 9 mm away on the back, which is what left HUB_DM4 open through two rounds (216c600b)
release: P2 retitled from P1 on its silk and its deliverable rebuilt, the first to pass all 35 properties of verify_deliverable (it had lost meshsat.pretty and the full BOM to the copy bug) (8559ef2d)
tools: the deliverable copy named two BOMs the same file, so under set -e the finish ended before meshsat.pretty and before verify_deliverable ever ran; every finish now tests finish_board.sh’s own status instead of tail’s (079e4dad)
tools: every board’s silk carries the phase its chain builds and the deliverable gate refuses another (P2 shipped stamped P1, D9 would have shipped stamped D8); solder wire lands are bench parts; the order index and the D legend rules drop the DMR858M, which left the device set on 6 September (6b5e9366)
tools: C8’s +5V rail carries its schematic loads in the intent and the RAIL class goes back to 0.5 mm (the lumped 0.6 A asked for 1.0 mm and the router wrote no session in 90 min or 3 h) (1e71fbf9)
tools: pair pre-router: hop layers carry only the dives and the stubs’ hops, never a corridor run (D9’s USB_D8 took 42 mm of In2 at 137 ohm); the chains name them (522ba958)
tools: pair pre-router: a via site is the cleared cell’s centre, not the polar sample beside it (b245aae1)
tools: pair pre-router: the dive tries the next via site when the stub into the pad finds no path (8a70e3e4)
tools: pair pre-router: the maps are rebuilt after an in-section swap and before the stub pass; the N fan runs 0.5 mm on before its turn when the P leg dives (afb0f0be)
tools: pair pre-router: the raster cache keys on the pad position (a swapped resistor kept its old raster and a stub shorted its pad), a pull-down across the other leg is stubbed by a dive; D9 R28 north of R27 clear of the crystal (27adeeff)
tools: pair pre-router: an SMD station’s corridor end sits where its own layer is free; the stub and via helpers live above the section loop (the stub pass found them undefined after a direct-leg section); the blocked direct leg is named in debug (c51c7b18)
tools: A23 VIN_RAW copper round the dock header’s second row on B.Cu, F.Cu and In3 (the riser through the row filled as two pieces); the D and C chains give the pre-router In2 as the dive layer (4b6b6b59)
tools: 33 LCSC codes that resolved to wrong or unstocked parts at JLCPCB corrected in the schematic generators and the fill table, codes only (owner ruling, appendix 32.72) (c93d6a30)
tools: D9: the USB1 resistor row 4.4 mm from the codec pad tips so both stations’ entry runs fit (2453ac6b)
tools: P intent names the current sinks (the mesh split 10 A over the sense pads); a stitch via outside the fill with no track is a note (3dc3d068)
tools: pair pre-router keeps the board minimum clearance between its legs; through-hole pin pairs are entry stations (5a9262ca)
tools: P2 power class 0.5 mm for the router’s sense and test-point links (the current is in the locked bands) (be023b77)
tools: the D9 profile’s nested names (95eac14f)
tools: routeflow routes in the profile’s project directory (a copy directory), the D9 finish and profile, the pair pre-router in the A chain (52bdf05e)
tools: jitter campaign: expand the profile’s tilde jar path, a 9999 score is no session (63813365)
tools: the jitter campaign moves the passives only and gets one directory per sample; pruned escapes warn in the predictor (ff673a6d)
tools: re-arm the gates of the audit 32.64: one hard set, ERC and zone nets block, contracts in every finish, deliverable read back, copper checks restored (c5880477)
tools: partition stage two: bash’s GROUPS is a read-only array, the group list is PARTS; the project file travels with every board (4deae0e3)
tools: cont_route kills only its own router (absolute session path) (fc5fb645)
tools: finish_b16 runs the DRC the knot removal reads (ef0cf20f)
ecad: ground pads of a part with an exposed pad join it along their own axis (the ring of 0.4 mm escape vias fences the plane on every layer); the C7 gate counts vias only where a keep-out forbids them (9fd73788)
ecad: D8 silk legend names the south edge for the PA leads (post-route text swap, deliverable rebuilt) (b1413ffa)
render: pigtails to the dock clamps under the battery row, the official MeshSat mark on the plate, dock views as cutaways (owner, 6 Sep 14:45) (727e9759)
face: the e-paper window moves up 8 mm so 8.6 mm of plate separates its lens pocket from the display glass pocket (owner, 6 Sep 14:45); plate set regenerated (4a4e90b2)
pcb-c: In1 stays a solid plane on C6 outside the two driver clusters (In1 track keep-outs with windows, the B15 pattern); gate checks them (89b6477e)
render: level views hide each board’s parts with it; the connector plate close-up from outside; 39 views (6302088c)
render: the 1450 lid sits on the rim (no 25.4 mm drop), antenna ports drawn as jacks with only the recorded Iridium patch and GNSS puck, the view set weighted to the inside (16819b1c)
tools: C6 profile back to the configuration that routed clean (2.4.1, In1 routable, no plane); the plane variants shorted or left opens (9ac8c0d1)
tools: autoroute settings go into the DSN, never a -dr file (it dropped the design’s clearances); the C gate’s via drill floor follows the layer count (8a6aa3fc)
pcb-c: the four-layer backer takes JLC’s 0.4/0.2 via floor (d2c2cde6)
tools: route_one kills only its own router (absolute session paths); a twin experiment’s clean-up killed B15’s routes (aa81ae4e)
tools: one experiment per project directory (project lock, fail closed); the B14 and B15 experiments get their own directories; driver groups (6c0289b7)
tools: routeflow reruns a route that died within a minute (tool failure, not a measurement); cloud box needs the full JRE for 1.9.0; JVM cap 5 GB (baf3a42b)
pcb-b: the pair report covers every differential pair, so the matcher meanders the DSI pairs too (598b4a29)
pcb-b: B15 finish uses the coarse stub grid for the long open connections (2d76fbec)
pcb-c: C6 route congestion: outer-edge keep-out band, a second placement region on the bottom strip, single-thread 80-pass route, coarse stub grid (c6b5b775)
tools: finish scripts report a stub router crash instead of filtering it away (d4770d83)
pcb-b: hole and nut keep-outs on every copper layer of the six-layer stack; route_audit via width by layer (e2989560)
pcb-c: C6 e-paper header along X at Y 108, sounder lands to the sides, sounder courtyard sized to the through-body (e6f77597)
pcb-c: C6 side strips to X 120 so the LED column clears the edge; the gate measures the LED dome and the plate outline (20ff5231)
pcb-c: BackerScrew footprint labels formatted, footprint self-test, the C chain stops when a generator does not save (4fd7a44c)
pcb-c: the C6 chain’s inner log no longer clobbers the run log (09f50011)
cad: the wall bulkheads are not stack (e5f1cea7)
pcb-b: In1 stays solid everywhere but under the CM5 breakout window, where both inner layers are needed (c5c9648c)
pcb-b: B14 PCIe pairs length-matched by meanders on PCIe_TX_N and PCIe_RX_P (0.00 mm), deliverable re-exported (052b3781)
tools: the clean flag of the A21 and B14 finishes ends with a newline and is read with cat (a bare read reported every clean board as open) (55b275e4)
pcb: A21 and D7 boards retitled to their phase and date, deliverables re-exported (86304eed)
tools: post-route title swap for a routed board; phase and date strings of the A, B and D generators brought to A21, B14 and D7 (aaaee5b3)
pcb-a: the gate accepts a column split by its own foot when every piece touches it (1c728e7d)
pcb-a: the gate reads each feed fill on its own layer (ecc2aaf8)
pcb-a: locked copper spines through the island necks and the inductor taps (8638a9af)
pcb-a: the output islands and inductor taps go to the router as planes instead of keep-outs (01878d35)
pcb-a: bus_a21 clears obstacles by their real via radius (33459787)
pcb-a: bus_a21 uses the KiCad 9 net code accessor (a327e138)
pcb-a: F.Cu keep-outs on the output and inductor islands, the converters’ enable line as a locked In1 bus, CELL_N link in the PWR class (f1aab2d5)
pcb-a: the bootstrap capacitors are moved after packing, not fixed twice (5154215e)
pcb-a: the south feed vias clear the fuse pin hole (12cb5b1a)
pcb-a: bootstrap capacitors under their converters, boost feet under the node bar only with In1 in parallel, B.Cu south segments (da4f9237)
pcb-a: boost feeds on In2 and B.Cu in parallel with a wide foot under the node bar, six tap vias per inductor, no keep-out on the rail taps (7bab96ad)
pcb-a: the PI corridor 2 mm further north, off R18’s LED rail pad (aa9947f3)
pcb-a: the comma a line comment swallowed in the boost feed list (d4bc0c9d)
pcb-b: the B14 finish refuses an open or dirty board (88749702)
pcb-a: the boost 1 In2 column clears U22’s BST1 escape via; pad entries under 0.7 mm are not links (bfa8a591)
pcb-a: A21 rail collectors north of the inductors, boost feeds on In2 with inductor tap islands, fanout ties locked, adjacency in the gate (752ce10c)
pcb-a: A21 rail bands north of the boost row with track keep-outs, a continuity gate on the routed board, bands out of the DSN again (65771ed1)
pcb-a: A21 top-side output islands on the three converters, stitched to the rail bands; the router keeps bands and islands as conduction areas (b3ae906d)
pcb-d: the V8 bands at distinct priorities (a zones_intersect note on the D7 deliverable) (cb577401)
pcb-a: the A21 bands overlap only at distinct priorities; the node’s fuse tap already covers F2 (ccd3c192)
pcb-a: the A chain fans the rails and boost inputs out into the bottom bands (8c3635d2)
pcb-a: A21 rails and boost inputs on bottom copper bands with their pads fanned out, classes at 1.0/0.8/0.6 mm, the sense line out of the bank class (6822e061)
pcb-d: boost loop pads fanned out into the B.Cu pours, CELL class 0.8 mm so the router closes the loop (3a513757)
pcb-a: the project-file class list carries the BANK clearance too (two literal lists) (795d8e99)
pcb-d: B.Cu pours carry V8 and VIN_CELL (the router could not close the 1.2 mm boost loop), the north region off the edge clearance (9238345d)
pcb-a: BANK class clearance 0.15 (the cell node meets 0.15 mm pad gaps on the LTC2954 and the escape stubs) (b7a492d7)
tools: net-class patterns emitted in both name forms on every board (the slash of root-sheet labels defeated them), six optimiser threads per route attempt, pattern coverage in the B gate (16b0166e)
pcb-d: the D gate reads slashed net names; the expander region 1 mm wider (047465d0)
tools: the M.2 socket rows take the tip-via escape scheme; envelope check to the courtyard (84538c8d)
pcb-d: D7 content checks only on the placed board and run again after placement; the new resistors in the core region (1f61909d)
pcb-b: the placement comment had swallowed six fixed connectors on the FIXED line (d2665516)
tools: escape stubs for fine-pitch connectors too (the M.2 socket), coarse J parts still skipped (86b6fb96)
pcb-b: M.2 socket placed with the card along +X (the placer centres the courtyard), the gate reads the slashed net names (2d60e3cb)
pcb-d: pull-downs on the channel-code inputs, stale D6 strings in the title block, comments and ASSEMBLY, the polled tty and the analogue-channel rule in PANEL (070e8b45)
pcb-b: the CM5 PCIe lane wired to the M.2 socket (it fell into the NC fallback), the card buck on the Pi rail by ruling, PCIe connectivity guard in the gate (fefbe465)
pcb-b: the two new rail flags placed on the power sheet; 32.37 clock label (1989ff54)
pcb-b: B14 M.2 site 3 mm east, clear of the LTE envelope (57e3e683)
release: E5 block with the underside legend inside the edge; order and review sets (f4e5fe15)
ecad: E5 underside legend moved inside the board edge (a1e73216)
release: E5 block with the moved legends; order and review sets (43d391e3)
ecad: E5 block legends shortened and moved off the board edge and the corner holes (1eb3111e)
release: E5 block rebuilt with the outlined power targets on the pulled footprint; order and review sets (43297966)
release: A20 and E4 relabelled GNSS post-route, E5 block with one outline around the power targets; deliverables, order and review sets rebuilt (7d4e5afb)
ecad: the E5 target footprint’s second silk ring removed as well (182fe352)
ecad: GNSS label in the dock generator and assembly table; E5 power targets outlined once instead of merged rings (1b1260dc)
pcb-b: B13 project board after the reordered finish (e6f05a44)
pcb-d: D6 at 0.14 mm class clearance and 0.20 mm hole clearance; the 0.4 mm escape branch also gated on the hole clearance (25995979)
tools: stub router keeps 0.3 mm hole to hole from every via and drilled pad, B13 finish cleans before the stub router and refills the planes before its check, the post-fix keeps T-junction feet (273a0712)
ecad: B13 post-route joins, the 0.4 mm escape scheme only on boards set up for it, J_LEDS1 clear of the 2x9 header on A20, D6 at the 0.127 clearance floor (43f50614)
pcb-b: restore C18 and C19 on the RockBLOCK channel (a comment had swallowed them); docs and records for the Compute Module 5 set (9c930b11)
ecad: keyed and D-flat holes carry a footprint keep-out past their routed outline instead of an unplated ring (27d2879d)
tools: clean-up keeps a track another track branches from; the seals DXF is one file (6bca38a5)
ecad: keyed and D-flat panel holes carry a copper-free ring past their routed outline for the router (9f2170da)
tools: C5 gate accepts the frame screws’ courtyard and the track-free gasket band (81c555b0)
ecad: C5 keyway toward the operator, gasket band closed to tracks, chain stops on a gate failure (8f423292)
tools: dangling-via clean-up keeps a via that a same-net track passes over (eb998e03)
tools: fan escape knees step 0.15 mm so long rows keep their splay length (256430f9)
tools: fine-pitch fan escapes nest their knees so a 0.4 mm row’s second pin clears the first pin’s turn (c45c39e3)
tools: fine-pitch escape fallback uses a 0.7 mm via row so the splays stay clear at shallow depth (6f541f36)
tools: fine-pitch escape retries shallower via rows when a neighbour sits past the row (f1616999)
tools: fine-pitch escapes are locked for the router and retry with a narrower lane rule when a neighbour sits past the row (e034f156)
tools: stub router starts an inner-layer source with its joining via (66e145eb)
tools: stub router drops the closing via on an inner-layer goal even when the path already changed layer (583fbbcc)
tools: zone gate flags only overlapping same-priority zones; the node riser gets its own priority (a69a5036)
tools: strict net lookup for zones only; chains stop on a failed placement; finish refuses an unrouted board (de348040)
ecad: pours resolve local-label nets, never a phantom; taps above bars; zone-net gate; per-board fab README (f2736fd4)
docs: APEM locks in the panel schematic text and order notes, serialisation wording per 32.21, solar accessory line (51684d9b)
case: template labels pinned to the sheet in the mirrored back-wall view (aa8f0377)
tools: stub router keeps the hole clearance rule off drilled pads; wall cut-out template generator (0812a7c6)
ecad: R58 and R19 back as statements, the inline comments had swallowed them (8e83a238)
ecad: 30 V polyfuse on the heating pad feed, crystal caps coded, one code per value (36e8ee15)
ecad: TPS2065C sits on a SOT-23-5 land, buyable JEITA values, crystal caps matched, SMCJ15A on the SMC land; LCSC codes for the respin values (5eb252fc)
release: handoff stops when a deliverable folder has not reached this clone (a6ed9122)
ecad: the B rails are labels like A’s, no power:+5V_M1 symbol exists (2bbece98)
ecad: B names its module rail +5V_M1 like A; contract check knows the cross-connector aliases (82831aa7)
ecad: dock block 43 x 25 with corner standoffs, split power bands and plated wire lands (31ba2e51)
ecad: inner layers stay routable on A19; E5 block gets plated wire lands and column tracks (07e0d5b7)
tools: escape reads net class clearances from the project file (142926d4)
tools: escapes keep the net class clearance between stubs of different nets (410956dd)
tools: escapes and fanout ignore rule areas that allow vias (923dc4a8)
ecad: A19 node copper as pre-route pours around the pins and jacks, no tracks on the inner layers, charger escapes restored (72369fca)
ecad: dock strip placement pass 3 (def96270)
ecad: block board fills its zones after a reload (db997789)
ecad: dock strip gate helper and placement pass 2 (bed722c8)
ecad: A19 placement round 5, charger regions north and south of the IC, escape skip list (9f6b6d27)
ecad: A19 placement round 4 (68942fee)
ecad: A19 placement round 3 (b8d0cf9a)
ecad: A19 placement round 2, sites clear of the GPS puck and its slots, regions resized (45878c8e)
ecad: A19 schematic emitter restored, dock block clear of the rod nut, site 2 allowed under the ribbon rectangle (930b9758)
ecad: drop the empty PCB-A feed section from the B12 schematic layout (e5de2dc3)
handoff: panel switch and coupler part numbers in the bench-fit strings of the order notes (d07fadd5)
handoff: order notes name the bench-fitted inductors and the dock connector, and list the parts left out of the JLC files (2f035266)
ecad: the grid router and the checked closer accept PTH pads (no layer in the DRC text); A17’s SDA gap was skipped (e07f770a)
ecad: node bars also avoid vias of other nets (A17 MEZZ_CELL column shorted two vias) (fe04e3fc)

Performance

pcb-c: the pre-lay is measured twice and declared for no board; C14’s board stands at 0 hard and 2 unrouted (b15cfceb)
pcb-a: A30 routes A29’s copper with the via-cost remedy from the first round (66f93c7a)
pcb-c: the rip-up cost measured at 10 and it is far worse, so C14 goes back to C11’s recipe (adb541bd)
pcb-b: the class-aware obstacle map is declared for B, worth +2 of 113 (4717445a)
pcb-b: the layer-change pre-lay test is measured, costs 14 pairs, and goes behind its own knob, off (595a7f4c)
pcb-b: the leg matcher is off by default: it costs B ten pairs and fits nothing on A (cbb92dcc)
pcb-a: a wider pair corridor, where USB_D8’s two legs come out matched by themselves (98bd0e14)
pcb-b: the corridor covers its own legs on B: 71 of 113 against 65 (82259637)
pcb-b: the corridor slack re-measured on today’s tools: 0.08 lays 65 of 113 where the declared 0.06 lays 54 (4e7dd1f2)
b: ten points of the corridor slack, and it is a curve rather than a scatter (325217e4)
b: the corridor slack swept again, 0.06 lays 57 of 113 against 47 (2353e42b)
pre-router: the stub search takes the compiled kernel, on where numba is (dd7b3059)
pre-router: the stub search can take the compiled kernel, off until measured (914efb4f)
pre-router: count the calls beside the seconds, and the stub search is the pass (0870f335)
pre-router: name the half of a pass that nothing had ever measured (26da0c40)
e: cap E’s optimiser, which ran 20 minutes past a completed autoroute (2dd431af)
e: raise E’s pass ceiling to 250, because the last open is a different net every round (539df3ea)
tools: straighten merged one junction per full re-index, which is what stopped E7’s finish (50529d56)
preroute: index the copper by net, because the per-pair pass was still walking the whole board (f9cfd25d)
preroute: count the board’s copper once instead of rebuilding it per pair (5b548a0d)
tools: the pre-router’s station matching stops being factorial above the cliff (93d22d80)
tools: the corridor search as a pure function of arrays, compiled, and tested against the original (7d2231f4)
tools: rasterise the pre-router’s occupancy maps with one vectorised point-in-polygon call (6c69b863)
tools: the pair pre-router gets a wall-clock budget per pair, so a pass always ends (2d03bbd1)
tools: pair pre-router rasterises each pad and zone once per grow value for the whole run (56b2a291)

revA (2026-09-03)

Features

v2: Rev A release, JLCPCB order folder and review prints (56e8b007)
v2: vendor reference CAD and datasheets (05f943c1)
v2: KiCad carrier set sources, generator tools and design records (8c57d215)
v1: tesseract and parallax build records and FreeCAD plate model (dcad104f)

V1: tesseract and parallax (built April 2026, records published 2026-09-03)

Two hand-built kits, bench and demo units, in use. They differ only in the satellite modem (tesseract: RockBLOCK 9603 SBD; parallax: RockBLOCK 9704 IMT).

As built

Raspberry Pi 5 with a Geekworm X1202 UPS, LilyGO T-Call A7670E cellular, u-blox GPS, Quansheng UV-K5(8) with an AIOC for APRS, ESP32-S3 LoRa for Meshtastic, RTL-SDR v4, ZigBee CC2652P, DCF77 receiver, 3.7 inch e-paper, Raspberry Pi Touch Display 2
Three HDPE plates on M3 rods in an IP67 case with SMA bulkheads
Per-kit BOM, GPIO pinouts, FreeCAD plate model and a build guide (parts, case drilling, plates, harness tables, provisioning, checks)